Patents by Inventor Takayoshi Fujishiro

Takayoshi Fujishiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9070550
    Abstract: A semiconductor device includes a transistor formed by dividing into a first and a second areas, a source electrode pad connected with a first source region formed in the first area and a second source region formed in the second area, a drain electrode pad connected with a first drain region formed in the first area and a second drain region formed in the second area and a connection line to connect a first gate line and a second gate line, where the connection line being provided in a same layer as the first gate line formed in the first area and the second gate line formed in the second area. A wiring for connecting between nodes of another circuit can be provided over the layer having the connection line provided therein and thus the size of a circuit chip can be reduced.
    Type: Grant
    Filed: August 18, 2007
    Date of Patent: June 30, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Daisaku Kobayashi, Takayoshi Fujishiro
  • Publication number: 20110233624
    Abstract: One aspect of the present invention is a semiconductor device includes: source and drain regions; a gate electrode formed on the source and drain regions; a sidewall formed on a side surface of the gate electrode; a first silicide film formed on the source and drain regions a predetermined distance away from the sidewall; and a second silicide film formed on the gate electrode a predetermined distance away from the sidewall.
    Type: Application
    Filed: March 18, 2011
    Publication date: September 29, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takayoshi FUJISHIRO
  • Publication number: 20080128830
    Abstract: A semiconductor device includes a transistor formed by dividing into a first and a second areas, a source electrode pad connected with a first source region formed in the first area and a second source region formed in the second area, a drain electrode pad connected with a first drain region formed in the first area and a second drain region formed in the second area and a connection line to connect a first gate line and a second gate line, where the connection line being provided in a same layer as the first gate line formed in the first area and the second gate line formed in the second area. A wiring for connecting between nodes of another circuit can be provided over the layer having the connection line provided therein and thus the size of a circuit chip can be reduced.
    Type: Application
    Filed: August 18, 2007
    Publication date: June 5, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Daisaku Kobayashi, Takayoshi Fujishiro