Patents by Inventor Takayoshi Katahira
Takayoshi Katahira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230089258Abstract: Stacked circuit board structures and methods of assembly are described. In an embodiment, a stacked circuit board structure includes first circuit board and a second circuit board including a plurality of pins mounted thereon, and the plurality of pins are secured in a plurality of receptacles that are coupled with the first circuit board to provide electrical connection between the first circuit board and the second circuit board.Type: ApplicationFiled: September 17, 2021Publication date: March 23, 2023Inventors: Lan H. Hoang, Takayoshi Katahira, Bilal Mohamed Ibrahim Kani, Kishore N. Renjan, Manoj Vadeentavida, Jing Tao
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Publication number: 20230078536Abstract: System-in-package modules that can provide a high level of functionality, are space efficient, and are readily manufactured. In an example, a high-functionality system-in-package module can include both a wireless circuit and an antenna. In an example, a space-efficient system-in-package module can include different vertical interconnect paths that can be used to connect the wireless circuit to the antenna. In an example, instead of being shaped as a traditional rectangular cuboid, a space-efficient system-in-package module can have a shape that more closely matches contours of an enclosure for an electronic device.Type: ApplicationFiled: June 3, 2022Publication date: March 16, 2023Applicant: Apple Inc.Inventors: Ali N. Ergun, Bilal Mohamed Ibrahim Kani, Chang Liu, Ethan L. Huwe, Jeffrey J. Terlizzi, Jerzy S. Guterman, Jue Wang, Kishore N. Renjan, Kyusang Kim, Lan H. Hoang, Mandar S. Painaik, Manoj Vadeentavida, Sarah B. Gysbers, Takayoshi Katahira, Zhiqi Wang
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Patent number: 10638608Abstract: Frames and other structures for system-in-package modules that may allow components on boards in the modules to communicate with each other.Type: GrantFiled: September 28, 2018Date of Patent: April 28, 2020Assignee: Apple Inc.Inventors: Lan H. Hoang, Raghunandan R. Chaware, Chang Liu, Takayoshi Katahira
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Patent number: 10624214Abstract: Readily manufactured structures for sealing or encapsulating devices in system-in-a-package modules, such that the modules are easily assembled, have a low-profile, and are space efficient. One example may provide readily manufactured covers for SIP modules. These modules may be easily assembled by attaching the cover to a top side of a substrate. These SIP modules may have a low-profile, for example when their height is reduced using one or more recesses in a bottom surface of a top of the recess, where the one or more recesses are arranged to accept one or more components. These SIP modules may be made space efficient by placing an edge of a cover near an edge of the substrate and connecting the plating of the cover using side plating on, or vias through, the substrate.Type: GrantFiled: February 11, 2016Date of Patent: April 14, 2020Assignee: Apple Inc.Inventors: Amir Salehi, Takayoshi Katahira, Vu T. Vo, Wyeman Chen, Chang Liu, Dennis R. Pyper, Steven Patrick Cardinali, Lan Hoang, Siddharth Nangia, Meng Chi Lee
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Patent number: 10602612Abstract: Stacked circuit board structures are described. In an embodiment, a plurality of vertical devices serves as electrical interconnections between the first circuit board and the second circuit board. In an embodiment, a plurality of vertical interconnects or pins serve as electrical interconnections between the first circuit board and the second circuit board. The vertical interconnects or pins may be arranged side-by-side with a plurality of vertical or horizontal devices.Type: GrantFiled: July 15, 2019Date of Patent: March 24, 2020Assignee: Apple Inc.Inventors: Lan H. Hoang, Takayoshi Katahira, Leilei Zhang, Raghunandan R. Chaware
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Patent number: 10334732Abstract: Connectors that allow system-in-package modules to connect to other circuits in an electronic device in an area-efficient manner.Type: GrantFiled: September 22, 2017Date of Patent: June 25, 2019Assignee: Apple Inc.Inventors: Lan H. Hoang, Takayoshi Katahira
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Patent number: 10292258Abstract: Vertical shielding and interconnect structures for system-in-a-package modules, where the vertical shielding and interconnect structures are readily manufactured and are space efficient.Type: GrantFiled: September 25, 2017Date of Patent: May 14, 2019Assignee: Apple Inc.Inventors: Lan H. Hoang, Takayoshi Katahira
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Publication number: 20190098762Abstract: Connectors that allow system-in-package modules to connect to other circuits in an electronic device in an area-efficient manner.Type: ApplicationFiled: September 22, 2017Publication date: March 28, 2019Applicant: Apple Inc.Inventors: Lan H. Hoang, Takayoshi Katahira
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Publication number: 20190082538Abstract: Frames and other structures for system-in-package modules that may allow components on boards in the modules to communicate with each other.Type: ApplicationFiled: September 28, 2018Publication date: March 14, 2019Inventors: Lan H. Hoang, Raghunandan R. Chaware, Chang Liu, Takayoshi Katahira
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Publication number: 20180049311Abstract: Vertical shielding and interconnect structures for system-in-a-package modules, where the vertical shielding and interconnect structures are readily manufactured and are space efficient.Type: ApplicationFiled: September 25, 2017Publication date: February 15, 2018Applicant: Apple Inc.Inventors: Lan H. Hoang, Takayoshi Katahira
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Publication number: 20160286647Abstract: Vertical shielding and interconnect structures for system-in-a-package modules, where the vertical shielding and interconnect structures are readily manufactured and are space efficient.Type: ApplicationFiled: March 24, 2016Publication date: September 29, 2016Applicant: Apple Inc.Inventors: Lan H. Hoang, Takayoshi Katahira, Chang Liu
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Publication number: 20160270213Abstract: Readily manufactured structures for sealing or encapsulating devices in system-in-a-package modules, such that the modules are easily assembled, have a low-profile, and are space efficient. One example may provide readily manufactured covers for SIP modules. These modules may be easily assembled by attaching the cover to a top side of a substrate. These SIP modules may have a low-profile, for example when their height is reduced using one or more recesses in a bottom surface of a top of the recess, where the one or more recesses are arranged to accept one or more components. These SIP modules may be made space efficient by placing an edge of a cover near an edge of the substrate and connecting the plating of the cover using side plating on, or vias through, the substrate.Type: ApplicationFiled: February 11, 2016Publication date: September 15, 2016Applicant: Apple Inc.Inventors: Amir Salehi, Vu T. Vo, Wyeman Chen, Chang Liu, Dennis R. Pyper, Steven Patrick Cardinali, Lan Hoang, Siddharth Nangia, Meng Chi Lee, Takayoshi Katahira
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Patent number: 7812261Abstract: There are provided a multilayer printed circuit board and a testing piece for the printed circuit board, including a substrate having an inner-layer conductor circuit and one or more outer-layer conductor circuits formed on the substrate with an insulating layer laid between the substrate and outer-layer conductor circuit, wherein a strain gauge having a resistive element held tight between resin films formed from polyimide or thermoplastic resin is buried in the substrate, and electrodes electrically connected to the resistive element are exposed to outside from the resin film and are electrically connected at exposed portions thereof to a viahole. Even if a crack is caused by an impact test to take place in the insulative resin layer, the resin film layers prevent the crack from spreading and thus the resistive element forming the strain gauge will not be ruptured.Type: GrantFiled: January 17, 2005Date of Patent: October 12, 2010Assignee: Ibiden Co., Ltd.Inventors: Takahiro Yamashita, Hirofumi Futamura, Akihide Ishihara, Takayoshi Katahira
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Publication number: 20070190846Abstract: There are provided a multilayer printed circuit board and a testing piece for the printed circuit board, including a substrate having an inner-layer conductor circuit and one or more outer-layer conductor circuits formed on the substrate with an insulating layer laid between the substrate and outer-layer conductor circuit, wherein a strain gauge having a resistive element held tight between resin films formed from polyimide or thermoplastic resin is buried in the substrate, and electrodes electrically connected to the resistive element are exposed to outside from the resin film and are electrically connected at exposed portions thereof to a viahole. Even if a crack is caused by an impact test to take place in the insulative resin layer, the resin film layers prevent the crack from spreading and thus the resistive element forming the strain gauge will not be ruptured.Type: ApplicationFiled: January 17, 2005Publication date: August 16, 2007Applicant: IBIDEN CO., LTDInventors: Takahiro Yamashita, Hirofumi Futamura, Akihide Ishihara, Takayoshi Katahira
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Patent number: 6096575Abstract: An optimum condition detection method for flip-chip bonding that facilitates simple detection of optimum pressure and heating temperature for flip-chip bonding implemented by use of bonding material is provided.Type: GrantFiled: August 26, 1999Date of Patent: August 1, 2000Assignee: Motorola, Inc.Inventors: Yoshio Okada, Takayoshi Katahira