Abstract: A power supply unit includes a communication unit and a control unit. The communication unit is capable of performing communication with a first processing unit group constituted of a plurality of processing units connected thereto. The control unit controls powers to the plurality of processing units through the communication so that the powers are turned on in an order corresponding to an order of connection and assigns, to the plurality of processing units, respectively, IDs of numbers corresponding to the order of turning-on of the powers each time the power is turned on.

Abstract: A power supply unit includes a communication unit and a control unit. The communication unit is capable of performing communication with a first processing unit group constituted of a plurality of processing units connected thereto. The control unit controls powers to the plurality of processing units through the communication so that the powers are turned on in an order corresponding to an order of connection and assigns, to the plurality of processing units, respectively, IDs of numbers corresponding to the order of turning-on of the powers each time the power is turned on.

Abstract: Provided is a technique of optimizing a virtual operation timing of a processor after emulation. In order to accurately estimate the number of bus access cycles after the emulation, the number of cycles required for an access when an instruction is issued from a processor (MIPS) is divided for each of factors, and the number of bus access cycles is estimated as the sum of the numbers of cycles required for the respective factors. For example, a BusArbiter object receives data indicating a substantial time required for execution of a request from a peripheral that executes the request from the MIPS and a current status of a DMA from a DMA controller, and informs the MIPS of the received data and the received status. The MIPS optimizes its own virtual operation timing in accordance with the substantial time.

Abstract: A clock supply circuit capable of supplying clock signals having different frequencies to processing circuits, simplifying the circuit configuration, and realizing a reduction of the power consumption only by using a low frequency external oscillator, wherein a reference clock is multiplied by a multiplication circuit to generate a multiplied clock, the multiplied clock is divided by a predetermined division ratio to generate a clock signal having a desired constant frequency by a receiving clock generating circuit, furthermore, a DSP clock generating circuit generates a clock signal having a variable frequency according to a processing load of a DSP in accordance with a judgment result of a load judgment circuit, so it is possible to supply a clock signal maintained synchronization with received signal as well as a clock signal having a frequency variably controlled in accordance with the processing load.

Abstract: A clock supply circuit capable of supplying clock signals having different frequencies to processing circuits, simplifying the circuit configuration, and realizing a reduction of the power consumption only by using a low frequency external oscillator, wherein a reference clock is multiplied by a multiplication circuit to generate a multiplied clock, the multiplied clock is divided by a predetermined division ratio to generate a clock signal having a desired constant frequency by a receiving clock generating circuit, furthermore, a DSP clock generating circuit generates a clock signal having a variable frequency according to a processing load of a DSP in accordance with a judgment result of a load judgment circuit, so it is possible to supply a clock signal maintained synchronization with received signal as well as a clock signal having a frequency variably controlled in accordance with the processing load.