Patents by Inventor Takayoshi Maeda

Takayoshi Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11971633
    Abstract: An electrode structure includes: a plurality of pixel electrodes arranged separately from each other; and a plurality of dielectric layers laminated in a first direction with respect to the plurality of pixel electrodes, in which the plurality of dielectric layers includes: a first dielectric layer that spreads over the plurality of pixel electrodes in a direction intersecting with the first direction; and a second dielectric layer that includes dielectric material having a refractive index higher than that of the first dielectric layer, sandwiches the first dielectric layer together with the plurality of pixel electrodes, and has a slit at a position overlapping space between pixel electrodes adjacent when viewed from the first direction.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: April 30, 2024
    Assignees: SONY SEMICONDUCTOR SOLUTIONS CORPORATION, SONY GROUP CORPORATION
    Inventors: Takashi Sakairi, Tomoaki Honda, Tsuyoshi Okazaki, Keiichi Maeda, Chiho Araki, Katsunori Dai, Shunsuke Narui, Kunihiko Hikichi, Kouta Fukumoto, Toshiaki Okada, Takuma Matsuno, Yuu Kawaguchi, Yuuji Adachi, Koichi Amari, Hideki Kawaguchi, Seiya Haraguchi, Takayoshi Masaki, Takuya Fujino, Tadayuki Dofuku, Yosuke Takita, Kazuhiro Tamura, Atsushi Tanaka
  • Patent number: 7399687
    Abstract: The present invention relates to a method for producing an epitaxial substrate having a III-V group compound semiconductor crystal represented by the general formula InxGayAlzN (wherein, x+y+z=1, 0?x?1, 0?y?1, 0?z?1) having reduced dislocation density, comprising a first step of covering with a mask made of a different material from the III-V group compound semiconductor so that only portions around points of the crystal constitute openings by using a III-V group compound semiconductor crystal having a plurality of projection shapes and a second step of growing the III-V group compound semiconductor crystal laterally by using the III-V group compound semiconductor crystal at the opening as a seed crystal. According to the present invention, an epitaxial substrate having a III-V group compound semiconductor crystal having low dislocation density and little warp is obtained.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: July 15, 2008
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yoshinobu Ono
  • Publication number: 20060172512
    Abstract: The present invention relates to a method for producing an epitaxial substrate having a III-V group compound semiconductor crystal represented by the general formula InxGayAlzN (wherein, x+y+z=1, 0?x?1, 0?y?1, 0?z?1) having reduced dislocation density, comprising a first step of covering with a mask made of a different material from the III-V group compound semiconductor so that only portions around points of the crystal constitute openings by using a III-V group compound semiconductor crystal having a plurality of projection shapes and a second step of growing the III-V group compound semiconductor crystal laterally by using the III-V group compound semiconductor crystal at the opening as a seed crystal. According to the present invention, an epitaxial substrate having a III-V group compound semiconductor crystal having low dislocation density and little warp is obtained.
    Type: Application
    Filed: March 4, 2004
    Publication date: August 3, 2006
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yoshinobu Ono
  • Patent number: 6946308
    Abstract: When a crystal layer of III-V Group nitride compound semiconductor is formed, a nitride compound semiconductor layer is first overlaid on a substrate to form a base layer and a III-V Group nitride compound semiconductor represented by the general formula InxGayAlzN (where 0?x?1, 0?y?1, 0?z?1, x+y+z=1) is epitaxially grown on the base layer by hydride vapor phase epitaxy at a deposition pressure of not lower than 800 Torr. By making the deposition pressure not lower than 800 Torr, the crystallinity of the III-V Group nitride compound semiconductor can be markedly improved and its defect density reduced.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: September 20, 2005
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yasushi Iyechika
  • Patent number: 6844574
    Abstract: Provided is a III-V compound semiconductor having a layer formed from a first III-V compound semiconductor expressed by the general formula InuGavAlwN (where 0?u?1, 0?v?1, 0?w?1, u+v+w=1), a pattern formed on the layer from a material different not only from the first III-V compound semiconductor but also from a second III-V compound semiconductor hereinafter described, and a layer formed on the first III-V compound semiconductor and the pattern from the second III-V compound semiconductor expressed by the general formula InxGayAlzN (where 0?x?1, 0?y?1, 0?x?1, x+y+z=1), wherein the full width at half maximum of the (0004) reflection X-ray rocking curve of the second III-V compound semiconductor is 700 seconds or less regardless of the direction of X-ray incidence. In the III-V compound semiconductor, which is a high quality semiconductor, the occurrence of low angle grain boundaries is suppressed.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: January 18, 2005
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Takayoshi Maeda, Yasushi Iyechika
  • Patent number: 6756246
    Abstract: A method for fabricating a GaN-based III-V Group compound semiconductor is provided that utilizes a regrowth method based on the HVPE method to form a second III-V Group compound semiconductor layer having a flat surface on a first III-V Group compound semiconductor layer formed with a mask layer. The method uses a mixed carrier gas of hydrogen gas and nitrogen gas to control formation of a facet group including at least the {33-62} facet by the regrowth, and conducting the regrowth until a plane parallel to the surface of the first III-V Group compound semiconductor layer is once annihilated, thereby fabricating a III-V Group compound semiconductor having low dislocation density.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: June 29, 2004
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yasushi Iyechika
  • Publication number: 20030211710
    Abstract: When a crystal layer of III-V Group nitride compound semiconductor is formed, a nitride compound semiconductor layer is first overlaid on a substrate to form a base layer and a III-V Group nitride compound semiconductor represented by the general formula InxGayAlzN (where 0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1) is epitaxially grown on the base layer by hydride vapor phase epitaxy at a deposition pressure of not lower than 800 Torr. By making the deposition pressure not lower than 800 Torr, the crystallinity of the III-V Group nitride compound semiconductor can be markedly improved and its defect density reduced.
    Type: Application
    Filed: March 26, 2003
    Publication date: November 13, 2003
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yasushi Iyechika
  • Publication number: 20030045017
    Abstract: A method for fabricating a GaN-based III-V Group compound semiconductor is provided that utilizes a regrowth method based on the HVPE method to form a second III-V Group compound semiconductor layer having a flat surface on a first III-V Group compound semiconductor layer formed with a mask layer. The method uses a mixed carrier gas of hydrogen gas and nitrogen gas to control formation of a facet group including at least the {33-62} facet by the regrowth, and conducting the regrowth until a plane parallel to the surface of the first III-V Group compound semiconductor layer is once annihilated, thereby fabricating a III-V Group compound semiconductor having low dislocation density.
    Type: Application
    Filed: March 26, 2002
    Publication date: March 6, 2003
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yasushi Iyechika
  • Patent number: 6503610
    Abstract: Provided is a method of producing a group III-V compound semiconductor having a low dislocation density without increasing the thickness of a re-grown layer, the method includes a re-growing process using a mask pattern, and threading dislocations in the re-grown layer are terminated by the voids formed on the pattern.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: January 7, 2003
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Takayoshi Maeda, Yasushi Iyechika
  • Publication number: 20010031385
    Abstract: Provided is a method of producing a group III-V compound semiconductor having a low dislocation density without increasing the thickness of a re-grown layer, the method includes a re-growing process using a mask pattern, and threading dislocations in the re-grown layer are terminated by the voids formed on the pattern.
    Type: Application
    Filed: March 23, 2001
    Publication date: October 18, 2001
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Takayoshi Maeda, Yasushi Iyechika
  • Patent number: 5332451
    Abstract: An epitaxially grown compound-semiconductor crystal comprising a substrate, a buffer layer formed directly or indirectly on the substrate, and an active layer formed on the buffer layer. The buffer layer comprises (A) a high-resistivity AlGaAs or AlGaInP layer doped with oxygen or/and a transition metal and, formed thereon, (B) a layer consisting of high-purity GaAs, InGaP, or AlGaAs.
    Type: Grant
    Filed: April 29, 1992
    Date of Patent: July 26, 1994
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Masahiko Hata, Noboru Fukuhara, Takayoshi Maeda
  • Patent number: 5064778
    Abstract: A vapor-phase epitaxial growth method for producing a Groups III-V compound semiconductor containing arsenic by vapor-phase epitaxial growth using arsenic trihydride as an arsenic source is disclosed, wherein said arsenic trihydride has a volatile impurity concentration of not more than 1.5 molppb on a germanium tetrahydride conversion. The resulting epitaxial crystal has a low residual carrier concentration and is applicable to a field effect transistor.
    Type: Grant
    Filed: January 30, 1990
    Date of Patent: November 12, 1991
    Assignee: Sumitomo Chemical Co., Ltd.
    Inventors: Takayoshi Maeda, Masahiko Hata, Noboru Fukuhara, Tadeshi Watanabe
  • Patent number: 4976216
    Abstract: In an apparatus for vapor-phase growth which comprises a reactor having an inlet for the introduction of the gas containing a source material on its top and a susceptor provided in the downstream portion of the reactor, the improvement wherein the susceptor is generally in a conical or polygonal pyramid form consisting of an upper rectifying portion and a lower substrate holding portion, with the diameter of the susceptor in its lower portion increasing by a greater degree than in its upper portion.
    Type: Grant
    Filed: November 10, 1988
    Date of Patent: December 11, 1990
    Assignee: Sumitomo Chemical Co., Ltd.
    Inventors: Takayoshi Maeda, Masahiko Hata, Yasunari Zempo, Noboru Fukuhara, Hiroaki Takata
  • Patent number: 4533987
    Abstract: A power supply system is disclosed in which each of the phases of a three phase AC source are rectified and inverted. During inversion high frequency signals are obtained corresponding to the phases of the AC source which are synchronized so that their zero cross points occur at the same time. The high frequency signals are superposed in series to produce an output signal for a load which has a constant power and diminished current distortion.
    Type: Grant
    Filed: November 9, 1982
    Date of Patent: August 6, 1985
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Yoshiaki Tomofuji, Takayoshi Maeda
  • Patent number: 4172108
    Abstract: Sialon, which is one of promising materials in the field of engineering ceramics, is prepared by mixing a silicon nitride precursor such as amino- or imino-silanes and an alumina precursor such as trialkoxy- or triacyloxy-aluminums or polyaluminoxanes to obtain a sialon precursor, and then heating the sialon precursor at a temperature of not lower than 1000.degree. C. either in an ammonium or inert gas atmosphere or under reduced pressures.
    Type: Grant
    Filed: December 14, 1977
    Date of Patent: October 23, 1979
    Assignee: Sumitomo Chemical Co., Ltd.
    Inventor: Takayoshi Maeda