Abstract: A semiconductor device includes a semiconductor substrate, a plurality of memory cells, a plurality of bit lines, and a plurality of source lines. The memory cells are located in the semiconductor substrate. Each of the memory cells includes a trench provided in the semiconductor substrate, an oxide layer disposed on a sidewall of the trench, a tunnel oxide layer disposed at a bottom portion of the trench, a floating gate disposed in the trench so as to be surrounded by the oxide layer and the tunnel oxide layer, and an erasing electrode disposed on an opposing side of the tunnel oxide layer from the floating gate. The bit lines and the source lines are alternately arranged on the memory cells in parallel with each other.

Abstract: A semiconductor device includes a substrate, an element formed in the substrate, an insulation film formed on the substrate, wiring layers, and an electrode pad. The wiring layers are multilayered and electrically coupled to the element through the insulation film. The electrode pad is electrically coupled to a top wiring layer of the wiring layers. The top wiring layer is configured to be a top wiring-electrode layer that doubles as an electrode layer disposed under the electrode pad. The electrode layer of the top wiring-electrode layer is disposed directly above the element. The electrode pad and the electrode layer are multilayered to form a pad structure.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of memory cells, a plurality of bit lines, and a plurality of source lines. The memory cells are located in the semiconductor substrate. Each of the memory cells includes a trench provided in the semiconductor substrate, an oxide layer disposed on a sidewall of the trench, a tunnel oxide layer disposed at a bottom portion of the trench, a floating gate disposed in the trench so as to be surrounded by the oxide layer and the tunnel oxide layer, and an erasing electrode disposed on an opposing side of the tunnel oxide layer from the floating gate. The bit lines and the source lines are alternately arranged on the memory cells in parallel with each other.

Abstract: A semiconductor device includes: a substrate; and wiring layers on the substrate. Each wiring layer includes: an interlayer insulation film having a wiring groove with a via hole; a copper wiring in the groove and the hole; an barrier metal layer between an inner wall of the groove with the hole and the copper wiring; and an upper barrier metal layer on the interlayer insulation film and covering an upper surface of the copper wiring. The barrier metal layer prevents a copper component in the copper wiring from diffusing into the interlayer insulation film. The copper wiring of an upper layer is electrically coupled with the copper wiring of a lower layer. The upper barrier metal layer of the lower layer prevents a copper component in the copper wiring of the lower layer from diffusing into the interlayer insulation film of the upper layer.

Abstract: A semiconductor device includes a substrate, an element formed in the substrate, an insulation film formed on the substrate, wiring layers, and an electrode pad. The wiring layers are multilayered and electrically coupled to the element through the insulation film. The electrode pad is electrically coupled to a top wiring layer of the wiring layers. The top wiring layer is configured to be a top wiring-electrode layer that doubles as an electrode layer disposed under the electrode pad. The electrode layer of the top wiring-electrode layer is disposed directly above the element. The electrode pad and the electrode layer are multilayered to form a pad structure.