Patents by Inventor Takayoshi Oosakaya

Takayoshi Oosakaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making semiconductor integrated circuit, pattern detecting method, and system for semiconductor alignment and reduced stepping exposure for use in same
    Patent number: 5432608
    Abstract: According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h-line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to Through-the-Lens method; in this case as a characteristic feature of the invention, the observation light taken out from below the reticle is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
    Type: Grant
    Filed: August 24, 1993
    Date of Patent: July 11, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Komoriya, Takao Kawanabe, Shinya Nakagawa, Takayoshi Oosakaya, Nobuyuki Iriki
  • Method of making semiconductor integrated circuit, pattern detecting method, and system for semiconductor alignment and reduced stepping exposure for use in same
    Patent number: 5260771
    Abstract: According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h-line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to a through-the-lens method; in this case as a characteristic feature of the invention, the, observation light is taken out from below the reticle and is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: November 9, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Komoriya, Takao Kawanabe, Shinya Nakagawa, Takayoshi Oosakaya, Nobuyuki Iriki
  • Method of making semiconductor integrated circuit, pattern detecting method, and system for semiconductor alignment and reduced stepping exposure for use in same
    Patent number: 5094539
    Abstract: According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h- line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to a through-the-lens method; in this case as a characteristic feature of the invention, the observation light is taken out from below the reticle and is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
    Type: Grant
    Filed: February 21, 1989
    Date of Patent: March 10, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Komoriya, Takao Kawanabe, Shinya Nakagawa, Takayoshi Oosakaya, Nobuyuki Iriki