Abstract: A single polarizer projector with a color switch and a projection method thereof, wherein the mean luminance of the inputted video signal is calculated so that the transmittance of the color switch can be controlled by the mean luminance in such a fashion that the transmittance is set to a maximum (100%) while setting the same to a low level (50%), thereby preventing unnatural blackening of relatively dark image for improving the contrast ratio.

Abstract: A single polarizer projector with a color switch and a projection method thereof, wherein the mean luminance of the inputted video signal is calculated so that the transmittance of the color switch can be controlled by the mean luminance in such a fashion that the transmittance is set to a maximum (100%) while setting the same to a low level (50%), thereby preventing unnatural blackening of relatively dark image for improving the contrast ratio.

Abstract: A single polarizer projector using a color switch (i.e., color filter) comprising an image processing circuit for the image scaling processing, a &ggr; correction circuit for &ggr; correction, a panel drive circuit for driving a reflection panel, a color switch drive circuit for driving a color switch for coloring according to the gradation on the reflection display panel, and a color switch, whereby the color switch drive circuit determines the mean luminance of the outputted picture element data (original image) which has undergone the image processing, and the white color or black color is inserted among the displayed gradation for each of the R, G and B colors according to the value of the mean luminance to expand the dynamic range of the image to be displayed.

Abstract: A data processing device contains art execution circuit and a data buffer circuit which stores one or more commands and/or one or more parameters which are prefetched, until each of the commands and parameters is read out by the execution circuit. The execution circuit inputs the oldest command stored in the data buffer circuit when an execution of a preceding command is completed, inputs one or more parameters stored in the data buffer circuit when the command input therein requests the parameters, and executes the command input therein, using the parameters when the parameters are input therein. The device further contains a circuit for detecting whether or not there is enough vacant space in the data buffer circuit in which a further command and/or a parameter can be stored, and another circuit for detecting a state of the data buffer circuit in which state the data buffer circuit does not store data including a command and/or a parameter, which is necessary for a next operation in the execution circuit.

Abstract: A semiconductor integrated circuit device includes a memory storing a microprogram used for controlling a desired function, a generator for generating an internal microprogram activating signal. A switching part selects either one of an external microprogram activating signal generated by an external device and the internal microprogram activating signal generated by the generator based on a first signal supplied from outside of the semiconductor integrated circuit device, thereby outputting a selected microprogram activating signal. A microaddress generator generates a microaddress of the microprogram stored in the memory. The microaddress generator is activated by the selected microprogram activating signal.

Abstract: A data control device which acquires the right to use a bus and performs data control includes a request circuit which selectively generates a plurality of request signals for acquiring the right to use corresponding buses. The plurality of request signals are based on attributes of data to be exchanged with an external device. The exchanged data includes data and commands.

Abstract: A direct memory access controller coupled to a system bus of a system for controlling data transfers through a channel includes the following. A request handler receives a transfer request generated by a device connected to the system bus. A transfer control information register stores transfer control information used for obtaining transfer control information necessary for executing the data transfer by a next transfer request supplied from the request handler. A temporary register stores the transfer control information necessary for processing the next transfer request. A transfer control information setting circuit generates the transfer control information necessary for processing the next transfer request on the basis of the transfer control information registered in the transfer control information register during the data transfer by the present transfer request and then renewing the transfer control information and-temporary registers with the generated transfer control information.

Abstract: A direct memory access controller adaptable to control a direct memory access transfer in a data processing system which includes at least a central processing unit and a system bus, comprises a register coupled to the system bus for outputting a transfer terminate request signal which instructs a normal termination when the central processing unit is operating and a write operation is carried out with respect to the register from the central processing unit, and a transfer termination part coupled to the register for stopping to accept a new transfer request signal or stopping to generate a transfer request signal responsive to the transfer termination request signal so as to make an instructed channel inactive.

Abstract: A microprogram branching method and apparatus generate a continue address by successively incrementing an address, generate a branch address by referring to a branch address table depending on predetermined branch conditions, where the branch address table prestores branch addresses, discriminate whether or not a branch is to be made depending on the predetermined branch conditions and obtaining a discrimination result, select the continue address normally and selecting the branch address when the discrimination result indicates that the branch is to be made, and output a data which is read out from an address of a main memory depending on the selected address, where the main memory prestores microprograms.

Abstract: A direct memory access controller coupled to a system bus for controlling a data transfer by a direct memory access comprises an internal bus, a data handler coupled to the system data bus and the internal bus for controlling an exchange of data between the system bus and the internal bus, a microsequencer which controls by microprograms parts of the direct memory access controller in units of one system clock cycle during one present transfer cycle, and a programmable logic array part supplied with a transfer request, a transfer mode information and at least portions of a transfer address and a byte count. The programmable logic array part is coupled to the internal bus and outputs control information required during a next transfer cycle during one transfer cycle which corresponds to a predetermined number of system clock cycles.

Abstract: A direct memory access controller coupled to a system bus of a system including a memory, for controlling a data transfer by a direct memory access, includes a register registering a code which designates one of a plurality of descriptor formats, each of which defines both the number and type of descriptors necessary for the data transfer by the direct memory access, a group of registers for registering descriptors defined in one of the descriptor formats which is selected by the code registered in the register, a controller for controlling the data transfer by the direct memory access in accordance with the descriptors defined in the selected one of the descriptor formats registered in the register.

Abstract: A data transfer control system controls a data transfer between a source and a destination by rearranging a data arrangement of a data which is made up of data units each made up of one or a plurality of bits, and comprises an input/output interface unit for inputting the data from the source and for outputting the data to the destination, a data swap circuit coupled to the input/output interface unit for rearranging a data arrangement of the data received from the source through the input/output interface unit in terms of the data unit and for rearranging a data arrangement of the data outputted to the destination through the input/output interface unit in terms of the data unit, a temporary register for temporarily storing the data with the rearranged data arrangement obtained from the data swap circuit, and a data swap control circuit coupled to the data swap circuit for controlling the rearranging of the data arrangement in the data swap circuit responsive to a transfer information which includes at least

Abstract: A programmable logic array includes a programmable logic array being precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto. The programmable logic array also includes a circuit connected to the programmable logic array, for holding the programmable logic array in a precharged state by setting the clock signal to a fixed level when the programmable logic array is not selected and for switching the programmable logic array to a discharged state by supplying the clock signal the programmable logic array when the programmable logic array is selected, so that the programmable logic array is discharged on the basis of the contents of the input data when selected.

Abstract: A data transfer controlling apparatus for direct memory access comprising one or more first microaddress registers, each of which registers stores microaddress information for program processing of the data transfer for a corresponding channel; a second microaddress register which stores microaddress information for program processing other than the program processing of the data transfer; a micro read only memory operatively connected to said first and second microaddress registers, for storing microinstructions and outputting a predetermined microinstruction in accordance with microaddress information read out from a selected one of the first microaddress registers and the second microaddress register; and an incremental element operatively connected to said first and second microaddress registers, for incrementing the value of the microaddress information read out from the selected one of the first microaddress registers and the second microaddress register, and for writing the incremented microaddress inf

Abstract: A semiconductor integrated circuit comprises an internal data bus, a first holding part for entering and holding data which are obtained from outside the semiconductor integrated circuit via the internal data bus, a reading part for reading out the data held in the first holding part and for outputting the read out data to the internal data bus, a second holding part for entering and holding the data which is read out by the reading part via the internal data bus, a third holding part for entering and holding test data which are obtained from outside the semiconductor integrated circuit bia the internal data bus, a discriminating part for comparing the data held in the second and third holding part and for obtaining a discrimination result based on whether the compared data coincide, and an output part for outputtting the discrimination result of the discrimination part of the outside of the semiconductor integrated circuit.