Patents by Inventor Takayoshi Watanabe

Takayoshi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040235207
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: June 23, 2004
    Publication date: November 25, 2004
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 6759258
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: July 6, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Publication number: 20030203521
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 30, 2003
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Patent number: 6566150
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: May 20, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Publication number: 20020182796
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Application
    Filed: June 17, 2002
    Publication date: December 5, 2002
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Patent number: 6455335
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: September 24, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Publication number: 20020129323
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: October 9, 2001
    Publication date: September 12, 2002
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 6305230
    Abstract: A connection device and test system is capable of stable, low load damage-free probing of devices under test, which have many pins with a narrow pitch. Furthermore in order to achieve high speed exchange of electrical signals or so-called high frequency electrical signals, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: October 23, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 6197603
    Abstract: Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: March 6, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Patent number: 5929133
    Abstract: Anti-bacterial film according to the present invention is suitable for use as food packaging wrap, and is given with the properties required for such film, such as a clinging property, transparency, and an anti-fogging property, as well as a high anti-bacterial property. The anti-bacterial film according to the present invention comprises, for 100 weight parts of PVC resin, 5 to 50 weight parts of a plasticizer, 0.3 to 3.0 weight parts of a stabilizer, 0.02 to 1.0 weight parts of hydrotalcite, 0.5 to 5.0 weight parts of an anti-fogging agent, and 0.02 to 2.0 weight parts of an anti-bacterial compound. The anti-bacterial compound may consist of a compound obtained by ion exchanging metallic ions of inorganic oxo-acid salt in the form of irregular particles having a particle diameter no more than 0.5 .mu.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: July 27, 1999
    Assignee: Hitachi Chemical Filtec, Inc.
    Inventors: Takayoshi Watanabe, Satoru Aoki, Shinichi Ohta, Katsuhiro Shirono, Atsushi Tanaka
  • Patent number: 5379765
    Abstract: An intrabronchial catheter has an inflatable balloon on which the bronchial ECG lead electrodes are mounted. Upon inserting the intrabronchial catheter into the trachea or bronchus of a human body, air is supplied to the balloon so that the balloon is stably retained in the trachea or bronchus, thereby bringing the bronchial ECG lead electrodes in close contact with the internal wall surface of the trachea or bronchus so as to effectively obtain a bronchial electrocardiogram or effect cardiac pacing.
    Type: Grant
    Filed: December 4, 1992
    Date of Patent: January 10, 1995
    Inventors: Nagao Kajiwara, Takayoshi Watanabe
  • Patent number: 5256247
    Abstract: A resistor material having at least chromium, silicon and oxygen, Cr.SiO.sub.2, contained in electronic integrated circuits, particularly in the case of an aluminum layer being on the material, is etched with a liquid etchant composition containing 1.92 to 2.64 mol/l of hydrochloric acid, 0.26 to 0.77 mol/l of phosphoric acid, 5 to 10 mol/l hydrofluoric acid and 3.2 to 5.4 mol/l of ammonium fluoride.
    Type: Grant
    Filed: November 21, 1991
    Date of Patent: October 26, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Takayoshi Watanabe, Takashi Inoue, Hitoshi Oka, Minoru Tanaka
  • Patent number: 4713494
    Abstract: A multilayer ceramic circuit board and method of forming such circuit board are disclosed. The wiring pattern for the multilayer ceramic circuit board includes multiple-layer portions, the multiple-layer portions including first and second electrically conductive layers, respectively a tungsten layer and a copper thick film, for example, with a diffusion layer therebetween for improving adhesivity of the first and second electrically conductive layers to each other. Such multiple-layer portions are provided by providing first and second electrically conductive layers, and an intermediate layer between the first and second electrically conductive layers, and diffusing at least one component from the intermediate layer into both the first and second electrically conductive layers. Thus, a multilayer ceramic circuit board with, e.g., a firmly coupled tungsten layer and copper thick film can be provided.
    Type: Grant
    Filed: April 14, 1986
    Date of Patent: December 15, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Shoji Oikawa, Hiroshi Yamagishi, Shigeru Saito, Tsuyoshi Fujita, Takayoshi Watanabe