Abstract: A calculator calculates an approximate value of a function Y=log (1+e?x) using input data x. In the calculator, a decoder outputs m-bit data that represents a value corresponding to the slope of a straight line, and further outputs intercept data of the straight line. The straight line interpolates the function Y=log (1+e?x) for an interval that includes the input data x as an X-value, and has a slope of ?2n. The intercept data represents Y-intercept of the straight line. A shifter shifts the input data x by |n| bits based on the m-bit data, and provides the resultant value as first term data.

Abstract: In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.

Abstract: A memory control apparatus for controlling the operation of a memory array in a serial memory employs a command control section for registering the bits of an instruction which is received as an externally supplied set of serial data in conjunction with a corresponding series of cycles of a clock signal, with each set of serial data formatted as a command data portion preceded by a start bit, whereby the shifting of the start bit into the MSB stage of the shift register is detected and used to terminate supplying the clock signal to the shift register, thereby eliminating the use of a counter circuit. Any additional clock signal cycle following shifting of the start bit into the MSB stage of the shift register is detected, so that operating errors caused by noise in the received clock signal can be reliably eliminated.

Abstract: In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.

Abstract: A memory control apparatus for controlling the operation of a memory array in a serial memory such as a serial EEPROM employs a command control section for registering in a shift register the bits of an instruction which is received as an externally supplied set of serial data in conjunction with a corresponding series of cycles of a clock signal, with each set of serial data formatted as a command data portion preceded by a start bit, whereby the shifting of the start bit into the MSB stage of the shift register is detected and used to terminate supplying the clock signal to the shift register, thereby eliminating the use of a counter circuit for such clock signal control.

Abstract: A calculator calculates an approximate value of a function Y=log (1+e−X) using input data x. In the calculator, a decoder outputs m-bit data that represents a value corresponding to the slope of a straight line, and further outputs intercept data of the straight line. The straight line interpolates the function Y=log (1+e−X) for an interval that includes the input data x as an X-value, and has a slope of −2n. The intercept data represents Y-intercept of the straight line. A shifter shifts the input data x by |n| bits based on the m-bit data, and provides the resultant value as first term data.