Patents by Inventor Takayuki Hisaka
Takayuki Hisaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967537Abstract: A semiconductor device, a leak detection device, an outer wall, and a separation wall are provided on a substrate. A first hollow structure in contact with the semiconductor device and a second hollow structure in contact with the leak detection device are separated by the separation wall and formed in a hermetically sealed state. At least a part of a portion of the leak detection device in contact with the second hollow structure is made of a corrodible metal or an alloy containing a corrodible metal. At least a part of the outer wall is in contact with the second hollow structure.Type: GrantFiled: November 13, 2018Date of Patent: April 23, 2024Assignee: Mitsubishi Electric CorporationInventor: Takayuki Hisaka
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Publication number: 20220044978Abstract: A device (2) is provided on an upper surface of the device substrate (1). A sealing frame (16) made of a non-electrolytic plating reactive catalyst metal is provided on the upper surface of the device substrate (1) and surrounds the device (2). An upper surface of the device substrate (1) and a lower surface of the cap substrate (10) are joined in a hollow state through the sealing frame (16). A plurality of electrodes (8,11,12) are connected to the device (2) and extended out of the device substrate (1) and the cap substrate (10). A metal film (20) is provided on an outer surface of the sealing frame (16) and not provided on the device substrate (1) and the cap substrate (10).Type: ApplicationFiled: March 6, 2019Publication date: February 10, 2022Applicant: Mitsubishi Electric CorporationInventors: Koichiro NISHIZAWA, Takayuki HISAKA
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Publication number: 20210313242Abstract: A semiconductor device, a leak detection device, an outer wall, and a separation wall are provided on a substrate. A first hollow structure in contact with the semiconductor device and a second hollow structure in contact with the leak detection device are separated by the separation wall and formed in a hermetically sealed state. At least a part of a portion of the leak detection device in contact with the second hollow structure is made of a corrodible metal or an alloy containing a corrodible metal. At least a part of the outer wall is in contact with the second hollow structure.Type: ApplicationFiled: November 13, 2018Publication date: October 7, 2021Applicant: Mitsubishi Electric CorporationInventor: Takayuki HISAKA
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Patent number: 11088074Abstract: A multi-finger transistor including plural control electrodes (2), plural first electrodes (3), and plural second electrodes (4) is provided on a semiconductor substrate (1). A resin film (14,15) covers the transistor. A first wiring (8) electrically connecting the plural first electrodes (3) to one other is provided on the resin film (14,15). The resin film (14,15) covers contact portions between the first wiring (8) and the plural first electrodes (3). A first hollow structure (16) sealed with the resin film (14,15) is provided around the plural control electrodes (2) and the plural second electrodes (4).Type: GrantFiled: April 4, 2017Date of Patent: August 10, 2021Assignee: Mitsubishi Electric CorporationInventors: Kazuhiro Maeda, Takayuki Hisaka, Hitoshi Kurusu
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Patent number: 10790397Abstract: A gate electrode (6) is provided on the semiconductor layer (2) and a least includes a lowermost layer (6a) in contact with the semiconductor layer (2), and an upper layer (6b) provided on the lowermost layer (6a). The upper layer (6b) applies stress to the lowermost layer (6a) to cause both edges of the lowermost layer (6a) to curl up from the semiconductor layer (2).Type: GrantFiled: February 27, 2017Date of Patent: September 29, 2020Assignee: Mitsubishi Electric CorporationInventors: Tasuku Sumino, Takayuki Hisaka
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Publication number: 20200020632Abstract: A multi-finger transistor including plural control electrodes (2), plural first electrodes (3), and plural second electrodes (4) is provided on a semiconductor substrate (1). A resin film (14,15) covers the transistor. A first wiring (8) electrically connecting the plural first electrodes (3) to one other is provided on the resin film (14,15). The resin film (14,15) covers contact portions between the first wiring (8) and the plural first electrodes (3). A first hollow structure (16) sealed with the resin film (14,15) is provided around the plural control electrodes (2) and the plural second electrodes (4).Type: ApplicationFiled: April 4, 2017Publication date: January 16, 2020Applicant: Mitsubishi Electric CorporationInventors: Kazuhiro MAEDA, Takayuki HISAKA, Hitoshi KURUSU
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Publication number: 20190378935Abstract: A gate electrode (6) is provided on the semiconductor layer (2) and a least includes a lowermost layer (6a) in contact with the semiconductor layer (2), and an upper layer (6b) provided on the lowermost layer (6a). The upper layer (6b) applies stress to the lowermost layer (6a) to cause both edges of the lowermost layer (6a) to curl up from the semiconductor layer (2).Type: ApplicationFiled: February 27, 2017Publication date: December 12, 2019Applicant: Mitsubishi Electric CorporationInventors: Tasuku SUMINO, Takayuki HISAKA
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Patent number: 10388585Abstract: A semiconductor device includes: a semiconductor substrate; a gate electrode on the semiconductor substrate; a SiN film on the semiconductor substrate and the gate electrode; and an oxide film on the SiN film, wherein the oxide film is an atomic layer deposition film including atomic layers alternately deposited.Type: GrantFiled: July 27, 2017Date of Patent: August 20, 2019Assignee: Mitsubishi Electric CorporationInventors: Takayuki Hisaka, Masahiro Totsuka, Tasuku Sumino
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Patent number: 10224294Abstract: Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.Type: GrantFiled: March 2, 2016Date of Patent: March 5, 2019Assignee: Mitsubishi Electric CorporationInventors: Koichiro Nishizawa, Takayuki Hisaka
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Publication number: 20180138132Abstract: Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.Type: ApplicationFiled: March 2, 2016Publication date: May 17, 2018Applicant: Mitsubishi Electric CorporationInventors: Koichiro NISHIZAWA, Takayuki HISAKA
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Publication number: 20180122718Abstract: A semiconductor device includes: a semiconductor substrate; a gate electrode on the semiconductor substrate; a SiN film on the semiconductor substrate and the gate electrode; and an oxide film on the SiN film, wherein the oxide film is an atomic layer deposition film including atomic layers alternately deposited.Type: ApplicationFiled: July 27, 2017Publication date: May 3, 2018Applicant: Mitsubishi Electric CorporationInventors: Takayuki HISAKA, Masahiro TOTSUKA, Tasuku SUMINO
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Patent number: 9627282Abstract: A method of manufacturing a semiconductor device includes: forming lower-layer wirings for a transistor, a circuit element and a plurality of contact pads on a substrate independently of each other; forming a first feed layer over an entire surface of the substrate on which the lower-layer wirings are formed; patterning the first feed layer to form a test pattern connecting terminals of the transistor to the separate contact pads independently of the circuit element; making a test on the transistor in a stand-alone state by using the contact pad and the test pattern; and after the test, connecting the transistor and the circuit element to form a circuit.Type: GrantFiled: April 5, 2016Date of Patent: April 18, 2017Assignee: Mitsubishi Electric CorporationInventors: Tasuku Sumino, Takayuki Hisaka, Takahiro Nakamoto
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Publication number: 20160343624Abstract: A method of manufacturing a semiconductor device includes: forming lower-layer wirings for a transistor, a circuit element and a plurality of contact pads on a substrate independently of each other; forming a first feed layer over an entire surface of the substrate on which the lower-layer wirings are formed; patterning the first feed layer to form a test pattern connecting terminals of the transistor to the separate contact pads independently of the circuit element; making a test on the transistor in a stand-alone state by using the contact pad and the test pattern; and after the test, connecting the transistor and the circuit element to form a circuit.Type: ApplicationFiled: April 5, 2016Publication date: November 24, 2016Applicant: Mitsubishi Electric CorporationInventors: Tasuku SUMINO, Takayuki HISAKA, Takahiro NAKAMOTO
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Patent number: 8766445Abstract: A semiconductor device includes: a semiconductor substrate; an underlying wiring on the semiconductor substrate; a resin film extending to the semiconductor substrate and the underlying wiring, and having a first opening on the underlying wiring; a first SiN film on the underlying wiring and the resin film, and having a second opening in the first opening; an upper layer wiring on the underlying wiring and part of the resin film; and a second SiN film on the upper layer wiring and the resin film, and joined to the first SiN film on the resin film. The upper layer wiring includes a Ti film, connected to the underlying wiring via the first and second openings, and an Au film on the Ti film. The first and second SiN films circumferentially protect the Ti film.Type: GrantFiled: June 18, 2012Date of Patent: July 1, 2014Assignee: Mitsubishi Electric CorporationInventors: Takayuki Hisaka, Takahiro Nakamoto, Toshihiko Shiga, Koichiro Nishizawa
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Publication number: 20130093061Abstract: A semiconductor device includes: a semiconductor substrate; an underlying wiring on the semiconductor substrate; a resin film extending to the semiconductor substrate and the underlying wiring, and having a first opening on the underlying wiring; a first SiN film on the underlying wiring and the resin film, and having a second opening in the first opening; an upper layer wiring on the underlying wiring and part of the resin film; and a second SiN film on the upper layer wiring and the resin film, and joined to the first SiN film on the resin film. The upper layer wiring includes a Ti film, connected to the underlying wiring via the first and second openings, and an Au film on the Ti film. The first and second SiN films circumferentially protect the Ti film.Type: ApplicationFiled: June 18, 2012Publication date: April 18, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takayuki HISAKA, Takahiro NAKAMOTO, Toshihiko SHIGA, Koichiro NISHIZAWA
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Publication number: 20090200644Abstract: A semiconductor device includes a semiconductor layer, an electrode connected to the semiconductor layer, a sacrificial metal layer connected to the electrode and made of a metal having higher ionization tendency than the material of the semiconductor layer and the material of the electrode.Type: ApplicationFiled: June 30, 2008Publication date: August 13, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Takayuki Hisaka
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Publication number: 20050167698Abstract: A semiconductor device includes a semiconductor substrate, a channel layer, a Schottky layer, a first layer having a narrower band gap than the Schottky layer, a second layer having band discontinuity with the Schottky layer, a gate electrode, an n+ layer, a source electrode, and a drain electrode. The first and second layers are within the Schottky layer, and the second layer is disposed on the first layer.Type: ApplicationFiled: March 14, 2005Publication date: August 4, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Takayuki Hisaka
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Patent number: 6876011Abstract: A semiconductor device includes a semiconductor substrate, a channel layer, a Schottky layer, a first layer having a narrow band gap than the Schottky layer, a second layer having band discontinuity with the Schottky layer, a gate electrode, an n+ layer, a source electrode, and a drain electrode. The first and second layers are within the Schottky layer, and the second layer is disposed on the first layer.Type: GrantFiled: September 12, 2003Date of Patent: April 5, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takayuki Hisaka
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Patent number: 5728611Abstract: A method of producing a semiconductor device includes preparing a semiconductor ingot having a (100) surface orientation and an orientation flat in a ?011! direction; cutting the semiconductor ingot in a plane which is obtained by tilting the (100) surface by an angle .theta. about an axis of the tilting, obtained by rotating the ?011! direction by an angle .phi. with the center of the (100) surface as an axis of the rotation, thereby producing a semiconductor wafer having a surface; producing a channel region in the semiconductor wafer; producing a refractory metal gate on the surface of the semiconductor wafer; and using the refractory metal gate as a mask, implanting dopant impurity ions into the semiconductor wafer in a direction perpendicular to the surface of the semiconductor wafer, thereby producing impurity-implanted regions in the semiconductor wafer. Channeling is prevented and the short-channel effect is suppressed.Type: GrantFiled: April 10, 1996Date of Patent: March 17, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takayuki Hisaka, Kenji Hosogi, Naohito Yoshida
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Patent number: 5677574Abstract: An airbridge wiring structure includes a substrate having a surface; a first wiring layer disposed on the surface of the substrate; and a second wiring layer disposed partially on the surface of the substrate and including an airbridge wiring layer crossing the first wiring layer, the first and second wiring layers being electrically insulated from each other and separated by an air gap wherein the airbridge wiring layer includes at least one longitudinal groove.Type: GrantFiled: April 9, 1996Date of Patent: October 14, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takayuki Hisaka