Abstract: When the same processing as initial training is executed to cope with fluctuation in the timing of a signal, the performance of a semiconductor device utilizing the relevant memory is degraded. A delay adjustment circuit adjusts a delay amount of write data to a memory device. A control circuit sets a delay amount of the delay adjustment circuit. A storage unit stores a delay amount. The control circuit corrects the delay amount stored in the storage unit based on a writing result of write data obtained when the delay amount stored in the storage unit or an amount based on that delay amount is set on the delay adjustment circuit.

Abstract: The present disclosure provides a semiconductor device that can achieve stable data communication with a simple method. The semiconductor device includes: a plurality of signal lines; a driver circuit that is provided corresponding to the signal lines and transmits a plurality of data in parallel by driving each of the signal lines; a plurality of delay circuits that are provided corresponding to each of the signal lines and can variably set the delay amount of data transmitted to the signal line; and a timing adjustment circuit for setting the delay amount of a corresponding signal line based on data of an adjacent signal line among the signal lines.

Abstract: When the same processing as initial training is executed to cope with fluctuation in the timing of a signal, the performance of a semiconductor device utilizing the relevant memory is degraded. A delay adjustment circuit adjusts a delay amount of write data to a memory device. A control circuit sets a delay amount of the delay adjustment circuit. A storage unit stores a delay amount. The control circuit corrects the delay amount stored in the storage unit based on a writing result of write data obtained when the delay amount stored in the storage unit or an amount based on that delay amount is set on the delay adjustment circuit.

Abstract: A data signal may not be fetched by using a data strobe signal if the waveform of the data is degraded with an increase in speed. In order to solve this problem, a first selection unit generates a first selection signal that indicates which one of a plurality of lanes Lane0 and Lane1 for transmitting a data signal that is input at a double data rate from the outside, based on a first strobe signal that is input from the outside. A gate unit sorts the data signal into any of the lanes Lane0 and Lane1 to output data signals Data1_0 and Data1_1, based on the first selection signal. Then, a latch unit latches the data signals Data1_0 and Data1_1 output to the lanes and outputs data signals Data2_0 and Data2_1.