Patents by Inventor Takayuki Imada
Takayuki Imada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10331474Abstract: A machine system includes a physical machine, a memory pool, and a memory pool management machine. The memory pool management machine manages, with respect to a memory region of the memory pool, an allocated region, a cleared region, and an uncleared region. When generating a virtual machine, a hypervisor in the physical machine sends a memory allocation request to the memory pool management machine. When a response, to the request, received from the memory pool management machine includes an address range belonging to the uncleared region, the hypervisor clears the memory region of the address range belonging to the uncleared region and then generates the virtual machine.Type: GrantFiled: January 8, 2016Date of Patent: June 25, 2019Assignee: Hitachi, Ltd.Inventors: Takayuki Imada, Toshiomi Moriki
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Patent number: 10114667Abstract: In a method of controlling a communication path among a plurality of virtual machines operating in one or more physical machines each of which includes one or more CPUs, memories, and I/O devices, allocating a virtual buffer serving as an alias of an actual buffer of a first virtual machine to a communication port that serves as a destination to which a communication path is changed from the first virtual machine and a second virtual machine directly or indirectly communicates with using a communication path change instruction as a trigger. Then, performing memory address translation on a region of the memory referred to by the virtual buffer, and generating the communication path between the first virtual machine and the second virtual machine by associating a region of the memory referred to by the first virtual machine and a region of the memory referred to by the second virtual machine.Type: GrantFiled: August 23, 2016Date of Patent: October 30, 2018Assignee: Hitachi, Ltd.Inventors: Kazuhiko Mizuno, Toshiomi Moriki, Takayuki Imada
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Publication number: 20180307518Abstract: A machine system includes a physical machine, a memory pool, and a memory pool management machine. The memory pool management machine manages, with respect to a memory region of the memory pool, an allocated region, a cleared region, and an uncleared region. When generating a virtual machine, a hypervisor in the physical machine sends a memory allocation request to the memory pool management machine. When a response, to the request, received from the memory pool management machine includes an address range belonging to the uncleared region, the hypervisor clears the memory region of the address range belonging to the uncleared region and then generates the virtual machine.Type: ApplicationFiled: January 8, 2016Publication date: October 25, 2018Inventors: Takayuki IMADA, Toshiomi MORIKI
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Patent number: 10057970Abstract: There is provided an ESD protection device capable of lowering a discharge starting voltage. An ESD protection device 1 includes a ceramic multilayer substrate 2, a first discharge electrode 4 and a second discharge electrode 5 arranged at a height position of the ceramic multilayer substrate, an end 4a of the first discharge electrode 4 and an end 5a of the second discharge electrode 5 facing each other, in which each of the first discharge electrode 4 and the second discharge electrode 5 contains a metal and a shrinkage suppression material having a lower rate of shrinkage than that of the metal at a temperature at which firing for the production of the ceramic multilayer substrate 2 is performed.Type: GrantFiled: October 26, 2015Date of Patent: August 21, 2018Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Takayuki Imada, Takayuki Tsukizawa, Jun Adachi
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Publication number: 20170277632Abstract: A hypervisor that allocates the computer resource of a physical computer to one or more logical partitions allocates the computer resource to be allocated to the logical partitions to the logical partitions; generates, as address conversion information, the relationship between a guest physical address and a host physical address with respect to a memory of the computer resource; enables a first address conversion portion of a processor using the address conversion information; disables the first address conversion portion after the starting of a guest OS is completed; and causes an application to be executed.Type: ApplicationFiled: October 30, 2014Publication date: September 28, 2017Applicant: Hitachi, Ltd.Inventors: Toshiomi MORIKI, Naoya HATTORI, Takayuki IMADA
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Patent number: 9698109Abstract: An ESD protection device 1 has a ceramic insulating material 10, first and second discharge electrodes 21 and 22, and a discharge-assisting section 51. The first and second discharge electrodes 21 and 22 are disposed somewhere of the ceramic insulating material 10. The discharge-assisting section 51 is located between the distal end portion of the first discharge electrode 21 and the distal end portion of the second discharge electrode 22. The discharge-assisting section 51 is an electrode configured to reduce the discharge starting voltage between the first discharge electrode 21 and the second discharge electrode 22. The discharge-assisting section 51 is made from a sintered body containing conductive particles and at least one of semiconductor particles and insulating particles. The first and second discharge electrodes contain at least one of the semiconductor material constituting the semiconductor particles and the insulating material constituting the insulating particles.Type: GrantFiled: February 6, 2015Date of Patent: July 4, 2017Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Takayuki Tsukizawa, Jun Adachi, Takayuki Imada, Takahiro Sumi
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Patent number: 9697024Abstract: A first processor group of physical processors having hardware-assisted virtualization set disabled among the plurality of physical processors; a second processor group of physical processors having the hardware-assisted virtualization set enabled among the plurality of physical processors; a first OS to which the first processor group is allocated; and a virtualization part to which the second processor group is allocated, the virtualization part is configured to: allocate a predetermined area within the memory and a predetermined one of the plurality of physical processors within the second processor group to the second OS as the virtualized processor, and boot the second OS to be provided as the virtual machine; and set a shared area, which is readable/writable by both the first OS and the virtualization part, and set interrupt routing information comprising a correspondence relationship between a logical interrupt to the second OS and a physical interrupt thereto.Type: GrantFiled: May 12, 2014Date of Patent: July 4, 2017Assignee: HITACHI, LTD.Inventors: Takayuki Imada, Toshiomi Moriki, Naoya Hattori
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Publication number: 20170123835Abstract: In a method of controlling a communication path among a plurality of virtual machines operating in one or more physical machines each of which includes one or more CPUs, memories, and I/O devices, allocating a virtual buffer serving as an alias of an actual buffer of a first virtual machine to a communication port that serves as a destination to which a communication path is changed from the first virtual machine and a second virtual machine directly or indirectly communicates with using a communication path change instruction as a trigger. Then, performing memory address translation on a region of the memory referred to by the virtual buffer, and generating the communication path between the first virtual machine and the second virtual machine by associating a region of the memory referred to by the first virtual machine and a region of the memory referred to by the second virtual machine.Type: ApplicationFiled: August 23, 2016Publication date: May 4, 2017Inventors: Kazuhiko MIZUNO, Toshiomi MORIKI, Takayuki IMADA
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Patent number: 9639486Abstract: A computer, having: a first OS to which a first processor core group is allocated; and a virtualization module to which a second processor core group is allocated, wherein a virtualization module registers interrupt handler processing for resetting the second processor core group, wherein a first OS has: a monitoring module for monitoring the virtualization module; and an interrupt control module for obtaining identifiers of the second processor core group at a time of booting of the virtualization module, and, when the monitoring module determines to reboot the virtualization module, issuing resetting interrupt to the processor cores of the second processor core group that are associated with the kept identifiers, wherein the second processor core group receives the resetting interrupt and executes the interrupt handler processing to reset its own processor cores, wherein the interrupt control module issues startup interrupt to the second processor core group.Type: GrantFiled: October 30, 2014Date of Patent: May 2, 2017Assignee: HITACHI, LTD.Inventors: Takayuki Imada, Toshiomi Moriki
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Patent number: 9495172Abstract: A computer system with a plurality of processors having a hardware-assisted virtualization and a memory, the computer system including a first processor group of the processors having hardware-assisted virtualization set disabled, and a second processor group of the processors and having hardware-assisted virtualization set enabled, the method having: booting a first OS by assigning the first processor group to the first OS; booting a virtual machine monitor to boot a virtual machine by assigning the second processor group to the virtual machine monitor; performed by the virtual machine monitor, booting a second OS by assigning a certain area of the memory to the second OS; and performed by the virtual machine monitor, setting a data path through which the first OS and second OS communicate with each other, the data path being set in the memory.Type: GrantFiled: April 15, 2014Date of Patent: November 15, 2016Assignee: Hitachi, Ltd.Inventors: Toshiomi Moriki, Takayuki Imada, Naoya Hattori
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Publication number: 20160044769Abstract: There is provided an ESD protection device capable of lowering a discharge starting voltage. An ESD protection device 1 includes a ceramic multilayer substrate 2, a first discharge electrode 4 and a second discharge electrode 5 arranged at a height position of the ceramic multilayer substrate, an end 4a of the first discharge electrode 4 and an end 5a of the second discharge electrode 5 facing each other, in which each of the first discharge electrode 4 and the second discharge electrode 5 contains a metal and a shrinkage suppression material having a lower rate of shrinkage than that of the metal at a temperature at which firing for the production of the ceramic multilayer substrate 2 is performed.Type: ApplicationFiled: October 26, 2015Publication date: February 11, 2016Inventors: Takayuki IMADA, Takayuki TSUKIZAWA, Jun ADACHI
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Publication number: 20150155246Abstract: An ESD protection device 1 has a ceramic insulating material 10, first and second discharge electrodes 21 and 22, and a discharge-assisting section 51. The first and second discharge electrodes 21 and 22 are disposed somewhere of the ceramic insulating material 10. The discharge-assisting section 51 is located between the distal end portion of the first discharge electrode 21 and the distal end portion of the second discharge electrode 22. The discharge-assisting section 51 is an electrode configured to reduce the discharge starting voltage between the first discharge electrode 21 and the second discharge electrode 22. The discharge-assisting section 51 is made from a sintered body containing conductive particles and at least one of semiconductor particles and insulating particles. The first and second discharge electrodes contain at least one of the semiconductor material constituting the semiconductor particles and the insulating material constituting the insulating particles.Type: ApplicationFiled: February 6, 2015Publication date: June 4, 2015Inventors: Takayuki Tsukizawa, Jun Adachi, Takayuki Imada, Takahiro Sumi
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Publication number: 20150120979Abstract: A computer, having: a first OS to which a first processor core group is allocated; and a virtualization module to which a second processor core group is allocated, wherein a virtualization module registers interrupt handler processing for resetting the second processor core group, wherein a first OS has: a monitoring module for monitoring the virtualization module; and an interrupt control module for obtaining identifiers of the second processor core group at a time of booting of the virtualization module, and, when the monitoring module determines to reboot the virtualization module, issuing resetting interrupt to the processor cores of the second processor core group that are associated with the kept identifiers, wherein the second processor core group receives the resetting interrupt and executes the interrupt handler processing to reset its own processor cores, wherein the interrupt control module issues startup interrupt to the second processor core group.Type: ApplicationFiled: October 30, 2014Publication date: April 30, 2015Applicant: Hitachi, Ltd.Inventors: Takayuki IMADA, Toshiomi MORIKI
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Publication number: 20150026678Abstract: A first processor group of physical processors having hardware-assisted virtualization set disabled among the plurality of physical processors; a second processor group of physical processors having the hardware-assisted virtualization set enabled among the plurality of physical processors; a first OS to which the first processor group is allocated; and a virtualization part to which the second processor group is allocated, the virtualization part is configured to: allocate a predetermined area within the memory and a predetermined one of the plurality of physical processors within the second processor group to the second OS as the virtualized processor, and boot the second OS to be provided as the virtual machine; and set a shared area, which is readable/writable by both the first OS and the virtualization part, and set interrupt routing information comprising a correspondence relationship between a logical interrupt to the second OS and a physical interrupt thereto.Type: ApplicationFiled: May 12, 2014Publication date: January 22, 2015Applicant: Hitachi, Ltd.Inventors: Takayuki IMADA, Toshiomi MORIKI, Naoya HATTORI
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Publication number: 20140359267Abstract: A computer system with a plurality of processors having a hardware-assisted virtualization and a memory, the computer system including a first processor group of the processors having hardware-assisted virtualization set disabled, and a second processor group of the processors and having hardware-assisted virtualization set enabled, the method having: booting a first OS by assigning the first processor group to the first OS; booting a virtual machine monitor to boot a virtual machine by assigning the second processor group to the virtual machine monitor; performed by the virtual machine monitor, booting a second OS by assigning a certain area of the memory to the second OS; and performed by the virtual machine monitor, setting a data path through which the first OS and second OS communicate with each other, the data path being set in the memory.Type: ApplicationFiled: April 15, 2014Publication date: December 4, 2014Applicant: Hitachi, Ltd.Inventors: Toshiomi MORIKI, Takayuki IMADA, Naoya HATTORI
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Publication number: 20130254767Abstract: A computer with a processor, memory, and one or more network interfaces, the computer having a virtualization management unit for managing a virtual computer and a bandwidth control unit for controlling a bandwidth in use in a virtual computer group comprised of one or more virtual computers, in which the virtualization management unit contains an analysis unit for managing a bandwidth in use of virtual network interfaces allocated to the virtual computers, the analysis unit measures the bandwidth in use of the each virtual computer, determines whether there exists a first virtual computer group whose bandwidth in use is smaller than a guaranteed bandwidth, and commands to control the bandwidth of a second virtual computer group whose bandwidth in use is larger than the guaranteed bandwidth, and the bandwidth control unit secures a free bandwidth just equal to a shortage of the guaranteed bandwidth of the first virtual computer group.Type: ApplicationFiled: February 6, 2013Publication date: September 26, 2013Applicant: Hitachi, Ltd.Inventors: Kazuhiko Mizuno, Takayuki Imada, Naoya Hattori, Yuji Tsushima