Patents by Inventor Takayuki Itoh

Takayuki Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220083033
    Abstract: An abnormality score calculation apparatus according to an embodiment includes a processing circuit configured to: acquire first data concerning a status of a product or a manufacturing process; calculate based on the first data an abnormality score for a respective one of a plurality of abnormality modes or for a respective one of a plurality of pieces of the first data of various types; and convert a scale of a respective one of a plurality of abnormality scores including the abnormality score in such a manner that the abnormality scores become substantially equal in occurrence degree.
    Type: Application
    Filed: February 26, 2021
    Publication date: March 17, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jumpei ANDO, Wataru WATANABE, Takayuki ITOH, Toshiyuki ONO
  • Publication number: 20220067514
    Abstract: According to one embodiment, an inference apparatus includes a processor. The processor generates an intermediate signal by processing an input signal with a convolutional neural network. The processor extracts one or more intermediate partial signals each serving as part of the intermediate signal from the intermediate signal. The processor calculates a statistic of the one or more intermediate partial signals. The processor outputs an inference result relating to the input signal and corresponding to the statistic.
    Type: Application
    Filed: February 22, 2021
    Publication date: March 3, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi IDA, Tenta SASAYA, Wataru WATANABE, Takayuki ITOH, Toshiyuki ONO
  • Publication number: 20220032201
    Abstract: A program, a control method, and an information processing apparatus capable of improving excitement of a game. An information processing apparatus (including a server device and a terminal device) executing a process of a game including game content for performing a battle using a plurality of game media may store the plurality of game media selected by a user of the game in association with the user, display some game media among the plurality of game media in a field area and proceed with the game content, and perform a process for providing a cooperation effect including changing of a parameter of a first game medium included in some game media when the first game medium satisfies a predetermined condition and a second game medium in a predetermined relationship with the first game medium and not included in some game media is included in the plurality of game media.
    Type: Application
    Filed: October 20, 2021
    Publication date: February 3, 2022
    Applicant: GREE, Inc.
    Inventors: Taku WATANABE, Norifumi OKUMURA, Takayuki ITOH, Kanji UEMURA, Naoko HANADA
  • Patent number: 11179642
    Abstract: A program, a control method, and an information processing apparatus capable of improving excitement of a game. An information processing apparatus (including a server device and a terminal device) executing a process of a game including game content for performing a battle using a plurality of game media may store the plurality of game media selected by a user of the game in association with the user, display some game media among the plurality of game media in a field area and proceed with the game content, and perform a process for providing a cooperation effect including changing of a parameter of a first game medium included in some game media when the first game medium satisfies a predetermined condition and a second game medium in a predetermined relationship with the first game medium and not included in some game media is included in the plurality of game media.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 23, 2021
    Assignee: GREE, Inc.
    Inventors: Taku Watanabe, Norifumi Okumura, Takayuki Itoh, Kanji Uemura, Naoko Hanada
  • Publication number: 20210295110
    Abstract: According to an embodiment, a processing apparatus includes a hardware processor. The hardware processor is configured to: cut out, from an input signal, a plurality of partial signals that are predetermined parts in the input signal; execute processing on the plurality of partial signals using neural networks having the same layer structure with each other to generate a plurality of intermediate signals including a plurality of signals corresponding to a plurality of channels; execute predetermined statistical processing on signals for each of the plurality of channels for each of the plurality of intermediate signals corresponding to the plurality of partial signals, to calculate statistics for each channel and generate a concatenated signal by concatenating the statistics of the plurality of respective intermediate signals for each channel; generate a synthetic signal by performing predetermined processing on the concatenated signal; and output an output signal in accordance with the synthetic signal.
    Type: Application
    Filed: August 28, 2020
    Publication date: September 23, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi Ida, Tenta Sasaya, Wataru Watanabe, Takayuki Itoh, Toshiyuki Ono
  • Patent number: 11043275
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first word line including a plurality of first cells and a second word line adjacent to the first word line and including a plurality of second cells. The memory controller determines a read voltage to be used with respect to the plurality of the first cells, according to a plurality of adjacent voltages representing respective threshold voltages of the plurality of the second cells. The memory controller reads data from the first word line using a plurality of determined read voltages.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: June 22, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Itoh, Tomoya Kodama
  • Publication number: 20210134032
    Abstract: A visualized data generation device includes an acquisitor, an analyzer, and a generator. The acquisitor acquires manufacturing data including one or more pieces of first data Yi regarding a product state with respect to one product. The analyzer analyzes the first data Yi acquired by the acquisitor and derives a first index value with respect to each piece of the first data Yi. The generator generates visualized data including a first analysis result display region for causing a display device to display information about the first index value. The generator generates the visualized data in which an amount of information and a priority is set for each first analysis result display region on the basis of the first index value and a display form of the first analysis result display region is set on the basis of the amount of information and the priority.
    Type: Application
    Filed: September 3, 2020
    Publication date: May 6, 2021
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Wataru WATANABE, Jumpei ANDO, Takayuki ITOH, Toshiyuki ONO
  • Publication number: 20210023446
    Abstract: When a mobile terminal obtains a container upon movement of a display range, a processor increases points in a storage unit. When the mobile terminal opens a container obtained by movement of the display range or as a present from another mobile terminal, the processor opens the container at predetermined success percentages, and writes an item obtained from the opened container in the storage unit. When the mobile terminal presents a container without opening it, the processor transmits screen data indicating a present to the other mobile terminal. The processor converts an item in the storage unit into points to increase the points in the storage unit based on an operation of the user of the mobile terminal.
    Type: Application
    Filed: October 14, 2020
    Publication date: January 28, 2021
    Applicant: GREE, Inc.
    Inventors: Takayuki ITOH, Tomohiro TSUKIHARA, Haruya NISHIKUBO, Midori MORIYAMA
  • Patent number: 10835817
    Abstract: When a mobile terminal obtains a container upon movement of a display range, a processor increases points in a storage unit. When the mobile terminal opens a container obtained by movement of the display range or as a present from another mobile terminal, the processor opens the container at predetermined success percentages, and writes an item obtained from the opened container in the storage unit. When the mobile terminal presents a container without opening it, the processor transmits screen data indicating a present to the other mobile terminal. The processor converts an item in the storage unit into points to increase the points in the storage unit based on an operation of the user of the mobile terminal.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: November 17, 2020
    Assignee: GREE, Inc.
    Inventors: Takayuki Itoh, Tomohiro Tsukihara, Haruya Nishikubo, Midori Moriyama
  • Patent number: 10649675
    Abstract: According to an embodiment, a storage controller comprises a circuitry configured to implement an address generator, a reader, and a duplication detector. The address generator is configured to generate a scan address indicating each storage area of a storage that stores therein externally written data, according to a particular scan pattern for defining an order of an address of data to be read. The reader is configured to read data from the storage area of the storage indicated by the scan address. The duplication detector is configured to detect whether the data read by the reader is a duplicate of any one of a past predetermined number of pieces of data.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoya Kodama, Takayuki Itoh, Katsuyuki Nomura
  • Publication number: 20200108318
    Abstract: A program, a control method, and an information processing apparatus capable of improving excitement of a game. An information processing apparatus (including a server device and a terminal device) executing a process of a game including game content for performing a battle using a plurality of game media may store the plurality of game media selected by a user of the game in association with the user, display some game media among the plurality of game media in a field area and proceed with the game content, and perform a process for providing a cooperation effect including changing of a parameter of a first game medium included in some game media when the first game medium satisfies a predetermined condition and a second game medium in a predetermined relationship with the first game medium and not included in some game media is included in the plurality of game media.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Applicant: GREE, Inc.
    Inventors: Taku WATANABE, Norifumi OKUMURA, Takayuki ITOH, Kanji UEMURA, Naoko HANADA
  • Patent number: 10600489
    Abstract: According to one embodiment, a memory system includes memory cells capable of having data written therein at different write levels. A memory controller is configured to detect first data of the memory cells, then apply a first voltage that is lower than a voltage used for writing the data to the plurality of memory cells, detect second data of the memory cells after the first voltage has been applied, and estimate a write level for the data written to the memory cells based on a comparison of the first data and the second data.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoya Kodama, Takayuki Itoh
  • Patent number: 10532289
    Abstract: A program, a control method, and an information processing apparatus capable of improving excitement of a game. An information processing apparatus (including a server device and a terminal device) executing a process of a game including game content for performing a battle using a plurality of game media may store the plurality of game media selected by a user of the game in association with the user, display some game media among the plurality of game media in a field area and proceed with the game content, and perform a process for providing a cooperation effect including changing of a parameter of a first game medium included in some game media when the first game medium satisfies a predetermined condition and a second game medium in a predetermined relationship with the first game medium and not included in some game media is included in the plurality of game media.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 14, 2020
    Assignee: GREE, Inc.
    Inventors: Taku Watanabe, Norifumi Okumura, Takayuki Itoh, Kanji Uemura, Naoko Hanada
  • Publication number: 20190279724
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first word line including a plurality of first cells and a second word line adjacent to the first word line and including a plurality of second cells. The memory controller determines a read voltage to be used with respect to the plurality of the first cells, according to a plurality of adjacent voltages representing respective threshold voltages of the plurality of the second cells. The memory controller reads data from the first word line using a plurality of determined read voltages.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 12, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki ITOH, Tomoya KODAMA
  • Publication number: 20190279728
    Abstract: According to one embodiment, a memory system includes memory cells capable of having data written therein at different write levels. A memory controller is configured to detect first data of the memory cells, then apply a first voltage that is lower than a voltage used for writing the data to the plurality of memory cells, detect second data of the memory cells after the first voltage has been applied, and estimate a write level for the data written to the memory cells based on a comparison of the first data and the second data.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 12, 2019
    Inventors: Tomoya KODAMA, Takayuki ITOH
  • Patent number: 10360101
    Abstract: According to one embodiment, a memory controller includes one or more processors configured to function as a writing unit and a reading unit. The writing unit writes data as threshold voltages of individual memory cells. The reading unit reads the written data by detecting threshold voltages of the individual memory cells. The reading unit includes a selecting unit, a detecting unit, and an estimating unit. The selecting unit selects a read-target memory cell. The detecting unit detects a first threshold voltage at a time of reading of the read-target memory cell, and a second threshold voltage at a time of reading of at least one of adjacent memory cells that are adjacent to the read-target memory cell. The estimating unit estimates a third threshold voltage as a threshold voltage at a time of writing in the read-target memory cell based on the first threshold voltage and the second threshold voltage.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoya Kodama, Takayuki Itoh, Atsushi Matsumura, Takuya Matsuo
  • Patent number: 10341660
    Abstract: According to an embodiment, a video compression apparatus includes a first compressor, a second compressor, a partitioner and a communicator. The first compressor compresses a first video to generate a first bitstream. The second compressor sets regions in a second video and compresses the regions so as to enable each region to be independently decoded, to generate a second bitstream. The partitioner partitions the second bitstream according to the set regions to obtain a partitioned second bitstream. The communicator receives region information indicating a specific region that corresponds to one or more regions and selects and transmits a bitstream corresponding to the specific region from the partitioned second bitstream.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: July 2, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akiyuki Tanizawa, Tomoya Kodama, Takeshi Chujoh, Shunichi Gondo, Wataru Asano, Takayuki Itoh
  • Patent number: 10306247
    Abstract: According to an embodiment, an image decoding apparatus includes a memory, a decoder and a first filter. The memory stores reference pixels based on pixels included in a decoded pixel block. The decoder decodes encoded data in units of pixel blocks using the reference pixels to generate a first decoded pixel block, the first decoded pixel block being adjacent to the reference pixels. The first filter performs a first filtering on only the first decoded pixel block using the first decoded pixel block and part of the reference pixels perpendicularly adjacent to the first decoded pixel block in a scan direction of image decoding processing.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 28, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takuya Matsuo, Takayuki Itoh, Takashi Watanabe, Atsushi Matsumura, Tomoya Kodama
  • Patent number: 10274853
    Abstract: A toner includes a binder resin; a release agent; and two or more inorganic fine particles as external additives. At least one of the inorganic fine particles is silica. When an ultrasonic oscillation is applied to a dispersion including the toner and a dispersant and a rate of the silica releasing from the toner is 20% based on total silica, an application energy of the ultrasonic oscillation is from 8 to 14 kJ, and from 70 to 130 kJ when the rate of the silica releasing from the toner is 50%.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: April 30, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Takayuki Itoh, Naohiro Watanabe, Takahiro Honda, Shingo Sakashita, Daisuke Inoue, Rintaro Takahashi, Ayumi Satoh
  • Publication number: 20190124343
    Abstract: According to an embodiment, an image decoding apparatus includes a memory, a decoder and a first filter. The memory stores reference pixels based on pixels included in a decoded pixel block. The decoder decodes encoded data in units of pixel blocks using the reference pixels to generate a first decoded pixel block, the first decoded pixel block being adjacent to the reference pixels. The first filter performs a first filtering on only the first decoded pixel block using the first decoded pixel block and part of the reference pixels perpendicularly adjacent to the first decoded pixel block in a scan direction of image decoding processing.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takuya MATSUO, Takayuki Itoh, Takashi Watanabe, Atsushi Matsumura, Tomoya Kodama