Abstract: This communication device comprises: a control circuit that measures signals received from a plurality of other communication devices to determine measurement values, and that generates, on the basis of the measurement values, feedback information relating to switching of cooperative communication; and a transmission circuit that transmits the feedback information.

Abstract: A method of producing a compound for bonded magnets, the method including: heat-curing a thermosetting resin and a curing agent having a ratio of the number of reactive groups of the curing agent to the number of reactive groups of the thermosetting resin of at least 2 but not higher than 11 to obtain an additive for bonded magnets; and kneading the additive for bonded magnets, magnetic powder, and a thermoplastic resin to obtain a compound for bonded magnets in which a filling ratio of the magnetic powder is at least 91.5% by mass.

Abstract: A sensor element includes a base part containing a solid electrolyte as a constituent material; at least one internal space into which a measurement gas is introduced; and at least one pump cell including an internal space electrode disposed to face the internal space, an out-of-space pump electrode disposed at a location other than the internal space, and a portion of the base part located between these electrodes, the internal space electrode includes a noble metal, the solid electrolyte, and a pore, and, in the internal space electrode, a ratio of a length of a boundary of a first region formed of the base part or the solid electrolyte contiguous with the base part and a second region occupied by the noble metal and the pore to a length of a boundary of the solid electrolyte and the internal space electrode is 1.1 or more.

Abstract: A sensor element includes: a base part containing an oxygen-ion conductive solid electrolyte as a constituent material; at least one internal space into which a measurement gas is introduced; and at least one pump cell including an internal electrode disposed to face the internal space, an out-of-space pump electrode disposed at a location other than the internal space, and a portion of the base part located between these electrodes, the internal electrode includes a noble metal, the solid electrolyte, and a pore, and, in the internal electrode, a degree of variation of a boundary of a first region formed of the base part or the solid electrolyte contiguous with the base part and a second region occupied by the noble metal and the pore in a thickness direction of the element is 0.5 ?m or more and 6.5 ?m or less.

Abstract: The present invention enables more efficient control of Multi-AP coordination. A base station, according to the present invention, comprises: a control circuit that generates shared information that is shared among a plurality of users and includes information pertaining to unassigned resources, and individual user information specific to each of the plurality of users; and a transmission circuit that transmits a control signal comprising the shared information and the individual user information.

Abstract: This communication device is provided with a control circuit for determining control information that corresponds to a control type set in inter-base station cooperative communication, and a transmission circuit for transmitting the control information.

Abstract: A semiconductor integrated circuit includes first and second circuits, a smoothing circuit, and a control circuit. The first circuit is configured to generate a first current with a power supply voltage and output the first current to an output terminal. The second circuit is configured to divide the power supply voltage and output a second current corresponding to a divided voltage to the output terminal. The second current is greater than the first current. The control circuit is configured to, in response to an enable signal, turn on the second circuit for a first period of time, during which the controller causes the first and second currents to be supplied to the output terminal, and in response to elapse of the first period of time, turn off the second circuit and cause the first current, and not the second current, to be supplied to the output terminal.

Abstract: According to one embodiment, in a semiconductor integrated circuit, a sampler is connected to an output node of a summer circuit. A shift register is connected to an output node of the sampler and includes K stages of registers, K being an integer that is equal to or larger than 3. To a control circuit, output nodes of respective registers of N-th to M-th stages among the K stages of registers are connected, N being an integer larger than 1 and smaller than K, M being an integer larger than N and equal to or smaller than K. A first switch includes one end connected to the output node of the summer circuit. A correction circuit includes a first control node that is connected to the control circuit through a first feedback line and an output node to which a second end of the first switch is connected.

Abstract: According to an embodiment, a regulator includes: a voltage control circuit to supply a voltage; a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; and a current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit make to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal.

Abstract: According to an embodiment, a regulator includes: a voltage control circuit to supply a voltage; a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; and a current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit make to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data output circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data output circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: According to one embodiment, a semiconductor memory device includes a memory core, a peripheral circuit which executes a reading/writing of data in the memory core, and an interface which inputs a control signal for the reading/writing. The control signal inputs by one data path. The peripheral circuit is configured to read a first data from a first address in the memory core in a first cycle, and read a second data from a second address in the memory core in parallel with writing a third data to a third address in the memory core in a second cycle.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data output circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data output circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.

Abstract: A semiconductor storage device includes: a memory cell array that includes a plurality of memory cells having a cell transistor formed on a well subjected to application of a predetermined substrate potential; a memory cell array control circuit that switches the number of memory cells, for use in storage of data of 1 bit in a normal operation state, to m (m is a natural number) and switches the number of memory cells, for use in storage of data of 1 bit in a standby state, to n (n is a natural number larger than m); and a substrate potential control circuit that controls the substrate potential in the normal operation state to a first substrate potential and controls the substrate potential in the standby state to a second substrate potential (the second substrate potential>the first substrate potential).

Abstract: A semiconductor storage device includes: a memory cell array that includes a plurality of memory cells having a cell transistor formed on a well subjected to application of a predetermined substrate potential; a memory cell array control circuit that switches the number of memory cells, for use in storage of data of 1 bit in a normal operation state, to m (m is a natural number) and switches the number of memory cells, for use in storage of data of 1 bit in a standby state, to n (n is a natural number larger than m); and a substrate potential control circuit that controls the substrate potential in the normal operation state to a first substrate potential and controls the substrate potential in the standby state to a second substrate potential (the second substrate potential>the first substrate potential).

Abstract: A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.

Abstract: A semiconductor memory device comprises a plurality of submacros mutually connected via global data lines. Each of the submacros includes a first and a second memory block, and a memory block control circuit arranged between the first and second memory blocks. The memory block control circuit includes a DQ buffer block connected to the first memory block via first complementary data lines and connected to the second memory block via second complementary data lines. It also includes a dynamic data shift redundancy circuit block connected to the DQ buffer block via local data lines and operative to relieve the first and second memory blocks.