Abstract: This wireless communication control device is a first wireless control device provided with: a control circuit that causes the waveform of a reference signal transmitted to a wireless communication device in coordination with a second wireless communication control device to differ, either in the frequency domain or the time domain, from the waveform of a reference signal transmitted to the wireless communication device by the second wireless communication control device; and a transmission circuit that transmits the reference signal.

Abstract: A base station according to the present invention is equipped with: a receiver circuit that receives control information pertaining to sharing a response signal to a downlink signal during coordinated communication between base stations; and a control circuit that, on the basis of the control information, controls the transmission of the response signal to another base station.

Abstract: According to one embodiment, in a semiconductor integrated circuit, a sampler is connected to an output node of a summer circuit. A shift register is connected to an output node of the sampler and includes K stages of registers, K being an integer that is equal to or larger than 3. To a control circuit, output nodes of respective registers of N-th to M-th stages among the K stages of registers are connected, N being an integer larger than 1 and smaller than K, M being an integer larger than N and equal to or smaller than K. A first switch includes one end connected to the output node of the summer circuit. A correction circuit includes a first control node that is connected to the control circuit through a first feedback line and an output node to which a second end of the first switch is connected.

Abstract: According to an embodiment, a regulator includes: a voltage control circuit to supply a voltage; a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; and a current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit make to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal.

Abstract: According to an embodiment, a regulator includes: a voltage control circuit to supply a voltage; a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; and a current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit make to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data output circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data output circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: According to one embodiment, a semiconductor memory device includes a memory core, a peripheral circuit which executes a reading/writing of data in the memory core, and an interface which inputs a control signal for the reading/writing. The control signal inputs by one data path. The peripheral circuit is configured to read a first data from a first address in the memory core in a first cycle, and read a second data from a second address in the memory core in parallel with writing a third data to a third address in the memory core in a second cycle.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data output circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data output circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.

Abstract: A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.

Abstract: A semiconductor storage device includes: a memory cell array that includes a plurality of memory cells having a cell transistor formed on a well subjected to application of a predetermined substrate potential; a memory cell array control circuit that switches the number of memory cells, for use in storage of data of 1 bit in a normal operation state, to m (m is a natural number) and switches the number of memory cells, for use in storage of data of 1 bit in a standby state, to n (n is a natural number larger than m); and a substrate potential control circuit that controls the substrate potential in the normal operation state to a first substrate potential and controls the substrate potential in the standby state to a second substrate potential (the second substrate potential>the first substrate potential).

Abstract: A semiconductor storage device includes: a memory cell array that includes a plurality of memory cells having a cell transistor formed on a well subjected to application of a predetermined substrate potential; a memory cell array control circuit that switches the number of memory cells, for use in storage of data of 1 bit in a normal operation state, to m (m is a natural number) and switches the number of memory cells, for use in storage of data of 1 bit in a standby state, to n (n is a natural number larger than m); and a substrate potential control circuit that controls the substrate potential in the normal operation state to a first substrate potential and controls the substrate potential in the standby state to a second substrate potential (the second substrate potential>the first substrate potential).

Abstract: A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.

Abstract: A semiconductor memory device comprises a plurality of submacros mutually connected via global data lines. Each of the submacros includes a first and a second memory block, and a memory block control circuit arranged between the first and second memory blocks. The memory block control circuit includes a DQ buffer block connected to the first memory block via first complementary data lines and connected to the second memory block via second complementary data lines. It also includes a dynamic data shift redundancy circuit block connected to the DQ buffer block via local data lines and operative to relieve the first and second memory blocks.

Abstract: A semiconductor storage device includes a normal area that contains a plurality of memory cells and a redundancy area that contains a plurality of memory cells. The semiconductor storage device further includes a delaying unit that changes, between a first mode in which both the normal area and the redundancy area are used and a second mode in which only the normal area is used without use of the redundancy area, a timing for issuing a cell-array control signal for selecting a memory cell from among the memory cells used in a corresponding mode.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of binary-data holding memory cells arranged at the intersections of the word lines and the bit lines; and a control unit operative to change in the storage capacity of the memory cell array and change in the address space required for access to the memory cell based on a control signal.

Abstract: A liquid crystal display comprises a liquid crystal panel (22), a group of optical sheets (32) disposed rearward from the liquid crystal panel (22), a light source (28) disposed rearward from the group of the optical sheets (32), a frame-shaped front frame (21, 23) disposed forward from at least the group of the optical sheets (32), a back chassis (31) disposed rearward from the light source (28) and fixedly connected to the front frame (21, 23) directly or indirectly, and a holding member (27) integrally holding the group of the optical sheets (32) to keep the group of the optical sheets (32) held in position integrally, when the back chassis (31) and the front frame (21, 23) are unfixed from each other.

Abstract: A semiconductor memory device comprises a plurality of submacros mutually connected via global data lines. Each of the submacros includes a first and a second memory block, and a memory block control circuit arranged between the first and second memory blocks. The memory block control circuit includes a DQ buffer block connected to the first memory block via first complementary data lines and connected to the second memory block via second complementary data lines. It also includes a dynamic data shift redundancy circuit block connected to the DQ buffer block via local data lines and operative to relieve the first and second memory blocks.

Abstract: A liquid crystal display comprises a liquid crystal panel (22), a group of optical sheets (32) disposed rearward from the liquid crystal panel (22), a light source (28) disposed rearward from the group of the optical sheets (32), a frame-shaped front frame (21, 23) disposed forward from at least the group of the optical sheets (32), a back chassis (31) disposed rearward from the light source (28) and fixedly connected to the front frame (21, 23) directly or indirectly, and a holding member (27) integrally holding the group of the optical sheets (32) to keep the group of the optical sheets (32) held in position integrally, when the back chassis (31) and the front frame (21, 23) are unfixed from each other.