Abstract: A face recognition device includes: an image capture unit, an area detection unit, a feature amount extraction unit, a distance estimation unit and a feature amount update unit. The image capture unit is configured to capture an image of an object. The area detection unit is configured to detect a given area of the object based on an image obtained as an image capture result of the image capture unit. The feature amount extraction unit is configured to extract a feature amount within the given area detected by the area detection unit. The distance estimation unit is configured to estimate a distance between the image capture unit and the given area. The feature amount update unit is configured to update the feature amount extracted by the feature amount extraction unit based on the distance estimated by the distance estimation unit.

Abstract: A multimedia data recording apparatus is disclosed that enables large-volume recorded data to be recorded for a long period in accordance with the importance of the data, by means of a simple configuration and simple processing, and without imposing a heavy load on the system. In this apparatus, a layer classification section classifies video data captured by a surveillance camera and input via a video processing section into a plurality of layers on a frame-by-frame basis according to importance. A data recording section assigns a file to each layer and records classified data in a data recording medium. If an information amount reduction section detects that the vacant capacity of the data recording medium has reached or fallen below a threshold value, it deletes a frame belonging to the lowest layer among the plurality of layers.

Abstract: Cameras that are related to an alarm and a time period of an image that each camera records are defined in advance, and at a time of alarm occurrence, management data is made with reference to the definition contents. A surveillance object's transfer path is presumed, and on the basis of this presumption, with each of cameras installed along the pathway, the time periods of the images that are to be associated with an event are each delayed and defined. By this, it is possible to record the suspicious behavior that the surveillance object demonstrates at the time of alarm occurrence and the suspicious behavior that the surveillance object demonstrates on its transfer path to a surveillance area as an event image. Furthermore, it is possible to narrow the time periods of images in which the surveillance object may be caught.

Abstract: A multimedia data recording apparatus is disclosed that enables large-volume recorded data to be recorded for a long period in accordance with the importance of the data, by means of a simple configuration and simple processing, and without imposing a heavy load on the system. In this apparatus, a layer classification section classifies video data captured by a surveillance camera and input via a video processing section into a plurality of layers on a frame-by-frame basis according to importance. A data recording section assigns a file to each layer and records classified data in a data recording medium. If an information amount reduction section detects that the vacant capacity of the data recording medium has reached or fallen below a threshold value, it deletes a frame belonging to the lowest layer among the plurality of layers.

Abstract: Cameras that are related to an alarm and the time period of the image that each camera records are defined in advance, and at the time of alarm occurrence, management data is made with reference to the definition contents. Surveillance object 231's transfer path 232 is presumed, and on the basis of this presumption, with each of cameras 203 to 205 installed along the pathway, the time periods of the images that are to be associated with an event are each delayed and defined. By this means, it is possible to record the suspicious behavior that surveillance object demonstrates at the time of alarm occurrence and the suspicious behavior that surveillance object 231 demonstrates on his transfer path to surveillance area 221 as an event image. Furthermore, it is possible to narrow down the time periods of images in which surveillance object 231 may be caught.

Abstract: MOS transistors connected to each other are electrically isolated at both ends of a transfer gate by an LOCOS oxide film, and the bottom surface in a trenched capacitor portion and the side wall of a trench between adjacent capacitors are electrically isolated. A leakage current can be reduced; so that a semiconductor device comprising a capacitor having a reduced occupied area and large capacitance can e obtained.

Abstract: A semiconductor memory device comprising memory cells having stacked capacitors has a stacked structure formed by the selective removal of a polycrystalline silicon film (15; 20) and a silicon oxide film (18a; 18), employing the same mask (14). A field effect transistor connected to a stacked capacitor has a gate electrode (20) formed of the above described polycrystalline silicon film. This polycrystalline silicon film (20) is formed on the major surface of a semiconductor substrate. The above described silicon oxide film (18) as an upper layer insulating film formed on the gate electrode (20) has a residual stress not more than 10.sup.9 dyn/cm.sup.2.

Abstract: A MOS type semiconductor memory device and a method of controlling the same device that can improve the lifetime (reliability) of a capacitor dielectric film is disclosed. In accordance with the MOS type semiconductor memory device, the cell plate (upper electrode 9) voltage V.sub.GG of the capacitor is set to be greater than zero and less than an arithmetic average of the maximum logic voltage V.sub.H and the minimum logic voltage V.sub.L applied to the storage node. The lifetime of the capacitor dielectric film is improved in comparison with a cell plate voltage of V.sub.H /2 when an ON (Oxidized Nitride) film is used as a capacitor dielectric film.

Abstract: MOS transistors connected to each other are electrically isolated at both ends of a transfer gate by an LOCOS oxide film, and the bottom surface in a trenched capacitor portion and the side wall of a trench between adjacent capacitors are electrically isolated. A leakage current can be reduced, so that a semiconductor device comprising a capacitor having a reduced occupied area and large capacitance can be obtained.

Abstract: A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.

Abstract: A semiconductor device comprises a P type semiconductor substrate (1) with a trench (12) formed on a main surface thereof. An N type drain region (15a) is formed at the bottom surface portion of the trench (12). An insulating layer (19c) is formed on the surface of the substrate (1) including a sidewall and the bottom surface of the trench (12), the layer having a hole (20b) whose bottom surface being at least the surface of the drain region (15a). A conductive layer (18) is formed on the insulating layer (19c) which is contact with the drain region (15a) at the bottom surface of the trench (12) through the hole (20b). The conductive layer (18) consititues a drain electrode. A gate (13) is interposed between the conductive layer (18) and the sidewall of the trench (12), formed along the sidewall of the trench (12) and insulated by the insulating layer (19c). An N type source region (15b) is formed on the surface of the substrate (1) including a portion of the sidewall of the trench (12).

Abstract: A semiconductor device having a plurality of conductive layers is disclosed. The device has first level conductors (9) formed spaced apart on a semiconductor substrate (1). The semiconductor substrate (1) is provided with impurity diffusion regions (11) in its major surface between adjacent first level conductors (9). A triple layer insulation formed of a pair of oxide layers (12, 14) and an silicon oxide layer (13) sandwiched between the oxide layers (12, 14) covers the semiconductor substrate (1) and the first level conductors (9) thereon. At least one contact hole (15) is formed to extend through the triple layer insulation to either the impurity diffusion region (11) in the semiconductor substrate (1) or the first level conductor (9) on the semiconductor substrate (1). A second level conductor (16, 17) is provided on the triple layer insulation and on the inner surrounding wall of the contact hole (15).

Abstract: A semiconductor memory device includes a trench formed along the circumference of a planar type memory capacitor, a gate insulating film and a memory cell plate being formed on the side wall of the trench, whereby the side wall of the trench is also used as a memory capacitor.At the bottom of the trench, a thick insulating film is formed to be a cell separating region.

Abstract: Grooves having a predetermined depth are formed on an insulating layer, and an electrode wiring layer is provided in the grooves of the insulating layer. The electrode wiring layer is formed to fill the grooves either completely or partially to a predetermined thickness on the inner wall surfaces of the grooves.

Abstract: A semiconductor integrated circuit with a wiring arrangement for high integration density. The arrangement is dispersed on a semiconductor substrate with a first wiring portion formed on the substrate and a second wiring portion formed on the substrate at a location adjacent to one edge of the first wiring portion. The first wiring portion has a groove or a plurality of indentations formed therein, preferably in the vicinity of the edge thereof that is closer to the second wiring portion, for preventing short-circuiting between the first and second wiring portions through parts of the edge of the first wiring portion which have expanded during a heat treatment.

Abstract: A substrate support structure for an ion implantation device comprises a plurality of substrate holders supporting sample substrates so that each sample substrate can be rotated around an axis perpendicular to its main surface and so that the angle of inclination of said main surface with respect to ion beams can be changed, a rotary drive for rotatively driving the sample substrates, an inclination angle adjuster for changing the angle of inclination of the sample substrate with respect to ion beams, and a rotary disk rotatably installed and supporting the plurality of substrate holders on the same circumference with the center at its rotary axis.

Abstract: A semiconductor device comprising a capacitor of a laminated structure and a method of manufacturing thereof, in which first conductive layer and second conductive layer of different materials or different compositions are stacked alternately with dielectric films interposed therebetween and the first conductive layers and the second conductive layers are interconnected respectively at a time by suitably combining a selective etching method and an anisotropic etching method.