Patents by Inventor Takayuki Minemaru

Takayuki Minemaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6570231
    Abstract: An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-channel region, a silicon gate electrode is formed in such a manner that its width is enlarged only in the boundary portion between the n-channel region and the p-channel region. After forming a side wall insulating film, an n-channel diffusion layer and a p-channel diffusion layer, a metal silicide layer is formed in a self-aligned manner on the surfaces of the silicon gate electrode, the n-channel diffusion layer and the p-channel diffusion layer.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: May 27, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Yasumi, Ichirou Matsuo, Toshiki Yabu, Mizuki Segawa, Kunitoshi Aono, Akihiko Ohtani, Takayuki Minemaru, Tadashi Fukumoto
  • Patent number: 5500812
    Abstract: A product P is calculated by multiplying a multiplicand X and a multiplier factor Y which are 16-bit fixed-point numbers and binary numbers in two's complement notation. Thus obtained product P is 31-bit length and the most significant bit thereof is a sign bit. Further, the product P is rounded down or rounded off to obtain a 16-bit rounded result PR. At this time, the 15-bit rounding data R to be added to the product P is changed according to the sign of the product P which is predicted so as to obtain respective rounded results which have the same absolute value from the two products which have different signs from each other and the same absolute value. In detail, in a case of rounding-down, "0000" and "TFFF" (both in hexadecimal numeral) are respectively generated as the rounding data when the product P is positive and when the product P is negative.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: March 19, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mana Saishi, Takayuki Minemaru
  • Patent number: 5400154
    Abstract: Image data is processed to enlarge and contract an original image, represented by the data, by P times in an X-axis direction while the data is subjected to interpolation. The letter P denotes an arbitrary positive rational number. It is supposed that each of regions among pixels of the original image is divided into sub areas having a number of N by M, that is, N in the X-axis direction and M in a Y-axis direction. The letter N denotes an arbitrary integer equal to or greater than 2. The letter M denotes an arbitrary integer equal to or greater than 1. An N-time interpolation enlarging device or step serves to execute an interpolation process determined by an original-image sub area corresponding to a pixel of an enlargement/contraction-resultant image while simultaneously generating a plurality of pieces of process-resultant data representing a part of an image enlarged from the original image by N times in the X-axis direction.
    Type: Grant
    Filed: November 13, 1992
    Date of Patent: March 21, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisashi Takayama, Mikio Fujiwara, Takayuki Minemaru, Satoshi Takayama