Abstract: A memory includes first cell layers respectively including first cells, and a second cell layer including dummy cells. A first wire is connected to the first cells arrayed in a first direction. A second wire is connected to the dummy cells arrayed in the first direction. A third wire is connected to the first cells and one of the dummy cells arrayed in a second direction. A fourth wire is connected to the third wires arrayed in a third direction. A first voltage is applied to a selected first wire when reading data from a selected first cell, and transmits a read data to a selected fourth wire connected to the selected first cell. A reference voltage is applied to a non-selected fourth wire. A second voltage is applied to a selected second wire provided with the dummy cell between the selected second wire and the non-selected fourth wire.

Abstract: There is provided a communication device which includes a determination section that determines propriety of a retransmission request on a basis of priority specified for each area within a frame in retransmission control, and a transmission section that generates retransmission request data, and makes transmission to another communication device, in a case where the retransmission request is permitted in the determination section.

Abstract: A semiconductor integrated circuit includes a plurality of sense amplifier units including a first group of sense amplifier units and a second group of sense amplifier units, a first data bus, a second data bus, a transfer circuit between the first data bus and the second data bus, and a data latch connected to the second data bus and to the first data bus through the transfer circuit and the second data bus. Each sense amplifier unit is connected to one of the bit lines. The first data bus is connected to each of the sense amplifier units in the first group. The second data bus is connected to each of the sense amplifier units in the second group. The transfer circuit controls the transfer of data between the first data bus and the second data bus in both directions.

Abstract: According to one embodiment, a memory device includes, a memory cell array including first to fourth sub-arrays, a first bit line coupled to the first sub-array and the second sub-array, a second bit line arranged side by side with the first bit line in a first direction and coupled to the third sub-array and the fourth sub-array, a third bit line arranged at a position different from the first bit line in a second direction and coupled to at least the second sub-array and the third sub-array, a fourth bit line arranged side by side with the third bit line in the first direction and coupled to the fourth sub-array, a first circuit electrically coupled to the first bit line and the second bit line, and a second circuit electrically coupled to the third bit line and the fourth bit line.

Abstract: A male connecting device for medical use 1 includes a male connector 10 having a cylindrical configuration and a threadedly engageable cylinder 20 rotatably coupled to the male connector 10. A male luer portion 11 of the male connector 10 and a female luer portion 2a of the female connector 2 are joined by turning the threadedly engageable cylinder 20 in a tightening direction T. The male connecting device 1 further includes a loosening prevention mechanism 40 that prohibits rotation of the threadedly engageable cylinder 20 in a loosening direction L with respect to the male connector 10. The loosening prevention mechanism 40 includes ratchet teeth 41 formed in an inner periphery of the threadedly engageable cylinder 20, an elastic leaf 42 formed in the male connector 10 and extends in a circumferential direction and an engageable claw 43 protruded from a free end of the elastic leaf 42 and engageable with the ratchet teeth 41.

Abstract: A treatment planning system is configured to create a treatment planning for radiotherapy and includes a processing device and a memory. The memory stores a plurality of calculation models, and the processing device uses at least two of the plurality of calculation models to calculate calculation values of biological effect indices representing an effect of radiotherapy with respect to a condition for radiotherapy, and searches for the condition so that at least two of the calculation values to be calculated approach a predetermined target value.

Abstract: A memory includes a cell array including first and second sub arrays including memory cells and simultaneously driven in a read or a write operation. First lines are connected to the cells corresponding to one of physical rows, where the physical row is the cells arranged in a first direction in the cell array. Second lines are connected to the cells arranged in a second direction intersecting with the first direction in the cell array. A decoder selects a selection line from among the first lines in accordance with a logical row address corresponding to each of the physical rows and applies a read voltage or a write voltage to the selection line. A sense amplifier detects data from the second lines. Logical row addresses corresponding to physical rows adjacent to a certain physical row among the physical rows differ between the first sub array and the second sub array.

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate and a capacitor that includes a first electrode extending in a first direction intersecting the semiconductor substrate and a second electrode facing the first electrode. A first conductive layer is above the capacitor and extends in a second direction. A semiconductor layer penetrates the first conductive layer in the first direction. A first conductor can be above or below the first conductive layer and electrically connected to the first conductive layer. A first insulating film is between the first conductive layer and the semiconductor layer. A second conductive layer extends in the second direction and is electrically connected to the first conductive layer via the first conductor.

Abstract: A connecting structure for medical use includes a male assembly 1 and a female connector 2. The male assembly 1 includes a male connector 10 and a threadedly engageable cylinder 20. A male luer portion 11 of the male connector 10 and a female luer portion 2a of the female connector 2 are joined by turning the threadedly engageable cylinder 20 in a tightening direction in a state where a female screw 21a of the threadedly engageable cylinder 20 and an engageable protrusion 2c of the female connector 2 are threadedly engaged with each other. A torque limiting mechanism 50 is disposed between an operation cylinder 30 mounted on an outer periphery of the threadedly engageable cylinder 20 and the threadedly engageable cylinder 20. Engageable teeth 51 are formed in an inner periphery of one end portion of the operation cylinder 30 over an entire periphery. A slit 54 is formed in one end portion of the threadedly engageable cylinder 20.

Abstract: A memory includes first cell layers respectively including first cells, and a second cell layer including dummy cells. A first wire is connected to the first cells arrayed in a first direction. A second wire is connected to the dummy cells arrayed in the first direction. A third wire is connected to the first cells and one of the dummy cells arrayed in a second direction. A fourth wire is connected to the third wires arrayed in a third direction. A first voltage is applied to a selected first wire when reading data from a selected first cell, and transmits a read data to a selected fourth wire connected to the selected first cell. A reference voltage is applied to a non-selected fourth wire. A second voltage is applied to a selected second wire provided with the dummy cell between the selected second wire and the non-selected fourth wire.

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

Abstract: A memory includes first lines arrayed along a surface of a substrate. Second lines are arrayed along the surface of the substrate either above or below the first lines and intersecting with the first lines. Resistance change memory cells are provided to correspond to intersection regions between the first lines and the second lines, respectively. First switching elements are arranged on a side of first ends of the first lines and transmitting a first voltage for writing or reading data to at least one memory cell among the memory cells. Second switching elements are arranged on a side of second ends of the first lines on an opposite side to the first ends and transmitting the first voltage to at least another one memory cell among the memory cells. The first switching elements and the second switching elements are connected to different ones of the first lines, respectively.

Abstract: A semiconductor integrated circuit includes a plurality of sense amplifier units including a first group of sense amplifier units and a second group of sense amplifier units, a first data bus, a second data bus, a transfer circuit between the first data bus and the second data bus, and a data latch connected to the second data bus and to the first data bus through the transfer circuit and the second data bus. Each sense amplifier unit is connected to one of the bit lines. The first data bus is connected to each of the sense amplifier units in the first group. The second data bus is connected to each of the sense amplifier units in the second group. The transfer circuit controls the transfer of data between the first data bus and the second data bus in both directions.

Abstract: An actuator device includes a locking displaceable element and a manual operation element that are displaceably disposed in a fixed portion. The locking displaceable element is displaceable to locked/unlocked positions. The manual operation element engages with the locking displaceable element and displaces the locking displaceable element to lock/unlocked positions via manual operation. The fixed portion includes locking displaceable element stoppers and manual operation element stoppers. The locking displaceable element includes locking displaceable element stopper abutment surfaces. The manual operation element includes manual operation element stopper abutment surfaces. When the manual operation element is operated, the manual operation element stopper abutment surfaces abut against the manual operation element stoppers by to stop displacement of the manual operation element before the locking displaceable element stopper abutment surfaces abutting against the locking displaceable element stoppers.

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

Abstract: A locking pin driving mechanism includes a motor, a preceding gear, a round gear, a feed screw and a slider. The feed screw is coaxially fixed to the round gear. A locking pin is mounted in the slider. A center axis of the locking pin and a center axis of the feed screw are each disposed in parallel with a center axis of a vehicle inlet. An interaxial distance between the center axis of the vehicle inlet and the center axis of the feed screw is set to be larger than an interaxial distance between the center axis of the vehicle inlet and the center axis of the locking pin.

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

Abstract: A memory includes first-lines, second-lines, and memory cells. Third-lines are provided to respectively correspond to groups each comprising m (m?2) lines of the first-lines. A first selector selects a certain one of the first-lines from the groups and to connect the selected first-lines to the third-lines corresponding to the groups. Fourth-lines correspond to the third-lines. A second selector selects one of the third-lines and to connect the fourth-line to the selected third-line. A third selector selects a certain one of the second-lines. A first driver applied a voltage to the fourth-line. A second driver is connected to the third selector. The first driver charges the third-line corresponding to the first-line selected from the groups via the fourth-line. The first and second selectors bring the selected first-line and the third-line corresponding the first-line to an electrically floating state. The second driver applies a voltage to the selected second-line.

Abstract: A memory includes first lines arrayed along a surface of a substrate. Second lines are arrayed along the surface of the substrate either above or below the first lines and intersecting with the first lines. Resistance change memory cells are provided to correspond to intersection regions between the first lines and the second lines, respectively. First switching elements are arranged on a side of first ends of the first lines and transmitting a first voltage for writing or reading data to at least one memory cell among the memory cells. Second switching elements are arranged on a side of second ends of the first lines on an opposite side to the first ends and transmitting the first voltage to at least another one memory cell among the memory cells. The first switching elements and the second switching elements are connected to different ones of the first lines, respectively.