Patents by Inventor Takayuki Morishige

Takayuki Morishige has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7940799
    Abstract: In order to cope with format conversion of user data, the bit rate value and VBV (Video Buffering Verifier) buffer size value in a sequence header of an input code and the VBV delay value in a picture header of the input code are modified to obtain an intermediate code (305 to 309), and additional information (300) is generated for distinguishing GOP (Group of Pictures) user data (307) from the other main data. A VBV buffer simulation is performed using this additional information (300) to multiplex the GOP user data in a picture user data region to a data amount such that the operation does not fail, whereby an output code is generated.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: May 10, 2011
    Assignee: Panasonic Corporation
    Inventors: Akihiro Watabe, Noboru Mizuguchi, Eiji Miyagoshi, Takayuki Morishige
  • Patent number: 7739437
    Abstract: A priority control value, which is smaller as the priority of access by each of requesters is higher, decreases with the lapse of time when an access request is issued. When the access is completed, the priority control value increases by a priority decrease value (PERIOD). When there is no access request, the priority control value decreases to a reference priority value (TMIN) and is then maintained at the reference priority value. Access permission is given to the one of the requesters issuing requests which has the smallest priority control value. As a result, proper arbitration is performed at a high speed with a simple hardware configuration.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: June 15, 2010
    Assignee: Panasonic Corporation
    Inventors: Akihiro Watabe, Takayuki Morishige, Yuichiro Aihara
  • Publication number: 20080263249
    Abstract: A priority control value, which is smaller as the priority of access by each of requesters is higher, decreases with the lapse of time when an access request is issued. When the access is completed, the priority control value increases by a priority decrease value (PERIOD). When there is no access request, the priority control value decreases to a reference priority value (TMIN) and is then maintained at the reference priority value. Access permission is given to the one of the requesters issuing requests which has the smallest priority control value. As a result, proper arbitration is performed at a high speed with a simple hardware configuration.
    Type: Application
    Filed: January 26, 2006
    Publication date: October 23, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Akihiro Watabe, Takayuki Morishige, Yuichiro Aihara
  • Publication number: 20060153290
    Abstract: In order to cope with format conversion of user data, the bit rate value and VBV (Video Buffering Verifier) buffer size value in a sequence header of an input code and the VBV delay value in a picture header of the input code are modified to obtain an intermediate code (305 to 309), and additional information (300) is generated for distinguishing GOP (Group of Pictures) user data (307) from the other main data. A VBV buffer simulation is performed using this additional information (300) to multiplex the GOP user data in a picture user data region to a data amount such that the operation does not fail, whereby an output code is generated.
    Type: Application
    Filed: February 2, 2004
    Publication date: July 13, 2006
    Inventors: Akihiro Watabe, Noboru Mizuguchi, Eiji Miyagoshi, Takayuki Morishige
  • Patent number: 6597810
    Abstract: An image processing device having a plurality of cores which attains more efficient memory access than conventionally attained. In the image processing device employing pipeline processing, a memory access section 20 executes data transfer between an operation section 10 including a plurality of cores each performing operation for image processing and an external memory 2. The memory access section 20 has an access schedule storage portion 22 which stores types of data transfers per stage, and executes data transfer between the operation section 10 and the external memory 2 in accordance with the storage contents of the access schedule storage portion 22. A system control section 30 sets the types of data transfers in the access schedule storage portion 22 at a stage preceding the stage at which the data transfers are executed.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: July 22, 2003
    Assignee: Matsushita Electrical Industrial Co., Ltd.
    Inventor: Takayuki Morishige
  • Publication number: 20020196855
    Abstract: An external memory interface in a DVMPEG converter inputs/outputs DV data, which has been decoded by a DV decoder, to/from an external memory. Moreover, a format converter receives data, which is read out from the external memory via the external memory interface, and converts the format thereof from a DV format to an MPEG format. Then, an MPEG encoder encodes the DV data whose format has been converted so as to produce MPEG data. Thus, it is possible to provide a DVMPEG converter having a small circuit scale.
    Type: Application
    Filed: May 7, 2002
    Publication date: December 26, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Miyagoshi, Akihiro Watabe, Takayuki Morishige, Noboru Mizuguchi