Abstract: A logical simulation system includes delay information operating part which receives a dispersion rule file in which information on dispersion in a chip having electrical and physical characteristics which influence the operation of an integrated circuit to be analyzed is described and which receives design information of the integrated circuit to prepare a delay information file in consideration of each influence of the information on the dispersion on the basis of the dispersion rule file and the design information; and logical simulation part which receives the design information and the delay information file to carry out a logical simulation of the integrated circuit.

Abstract: The processing for deciding the remedy as being possible or impossible and the processing for remedying bit fails can be both executed in a short time on the basis of bit mask processing. Fail data are transferred from the tester to the redundancy processor (in Step S101), and the number of the fail addresses stored in the buffer memory is compared with the maximum number of fail bits (in Step S103). Further, the line fail detection and the remedy processing are both executed (in Step S105), and the redundancy processor decides whether the number of the line fails exceeds the number of the spare rows and the number of the spare columns or not (in Step S107). Further, the bit mask processing is executed for the fail addresses (in Step S109) to decide the remedy possibility (in Step S111). Here, the maximum remediable number of the bit mask processings can be calculated on the basis of "the number of row spares R+the number of the column spares".