Patents by Inventor Takayuki Nakai

Takayuki Nakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8747787
    Abstract: Provided is a method for producing ferronickel from a nickel sulfide or a mixed sulfide containing nickel and cobalt, obtained by hydrometallurgy of nickel oxide ore or obtained from scraps or products in process. The method for producing a ferronickel raw material is to form the ferronickel raw material from a nickel sulfide or a mixed sulfide containing nickel sulfide and cobalt sulfide, wherein treatments are performed through the following steps: (1) redissolution step, (2) deferrization step, (3) solvent extraction step, (4) hydroxylation step, (5) roasting step, and (6) washing and calcining step.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: June 10, 2014
    Assignee: Sumitomo Metal Mining Co., Ltd.
    Inventors: Hiroshi Kobayashi, Osamu Nakai, Keisuke Shibayama, Takayuki Nakai, Yoshitomo Ozaki, Norihisa Toki, Junichi Takahashi, Toshirou Tan
  • Publication number: 20130074653
    Abstract: Provided is a method for producing ferronickel from a nickel sulfide or a mixed sulfide containing nickel and cobalt, obtained by hydrometallurgy of nickel oxide ore or obtained from scraps or products in process. The method for producing a ferronickel raw material is to form the ferronickel raw material from a nickel sulfide or a mixed sulfide containing nickel sulfide and cobalt sulfide, wherein treatments are performed through the following steps: (1) redissolution step, (2) deferrization step, (3) solvent extraction step, (4) hydroxylation step, (5) roasting step, and (6) washing and calcining step.
    Type: Application
    Filed: July 13, 2011
    Publication date: March 28, 2013
    Applicant: SIMITOMO METAL MINING CO., LTD.
    Inventors: Hiroshi Kobayashi, Osamu Nakai, Keisuke Shibayama, Takayuki Nakai, Yoshitomo Ozaki, Norihisa Toki, Junichi Takahashi, Toshirou Tan
  • Publication number: 20110267014
    Abstract: An electrical load drive device can reduce the offset voltage without requiring means of initializing the charge of an integrating capacitance or a terminal for offset correction. The input selector of the electrical load drive device selects an input signal or no signal, and outputs an input selection signal. An integrator integrates the input selection signal and outputs the integrated signal. The load driver produces a load drive signal by pulse width modulation and amplification of the integrated signal. A first path is a path for feeding back the load drive signal. A second path is a path for feeding back the integrated signal. The path selector produces a feedback signal by selecting the first path or the second path. The offset correction signal generator produces an offset correction signal for adjusting the integrated signal so that the feedback signal offset decreases.
    Type: Application
    Filed: July 12, 2011
    Publication date: November 3, 2011
    Inventor: Takayuki NAKAI
  • Patent number: 7982541
    Abstract: A count control signal generating section for generating a count control signal on the basis of an output signal of a variable gain amplifier; an up/down counter for performing an up-count operation or a down-count operation on the basis of the count control signal; a gain control signal generating section for generating a gain control signal to be supplied to the variable gain amplifier on the basis of a count value of the up/down counter; and a state detector section for outputting a state detection signal indicating whether a state of a circuit operation is a steady state or another state are provided. When the state detection signal indicates that the state of the circuit operation is the steady state, the operation of at least one of the up/down counter and the gain control signal generating section is controlled so as to fix the gain control signal.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Takayuki Nakai, Takuma Ishida
  • Patent number: 7944276
    Abstract: A pumping circuit includes: a pumping capacitance; a first drive transistor connected between an input node for receiving an input voltage and one terminal of the pumping capacitance; and a second drive transistor connected between an output node for outputting an output voltage and the one terminal of the pumping capacitance. In a charge storing mode, the first drive transistor is turned ON to store charge in the pumping capacitance, while in a charge transfer mode, the second drive transistor is turned ON to transfer the charge stored in the pumping capacitance to the output node. The protection circuit puts at least one of the first and second drive transistors in a high-resistance state in which the resistance value is higher than when the transistor is ON, based on whether the output voltage is higher or lower than a predetermined judgment voltage.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: May 17, 2011
    Assignee: Panasonic Corporation
    Inventor: Takayuki Nakai
  • Publication number: 20100259330
    Abstract: A count control signal generating section for generating a count control signal on the basis of an output signal of a variable gain amplifier; an up/down counter for performing an up-count operation or a down-count operation on the basis of the count control signal; a gain control signal generating section for generating a gain control signal to be supplied to the variable gain amplifier on the basis of a count value of the up/down counter; and a state detector section for outputting a state detection signal indicating whether a state of a circuit operation is a steady state or another state are provided. When the state detection signal indicates that the state of the circuit operation is the steady state, the operation of at least one of the up/down counter and the gain control signal generating section is controlled so as to fix the gain control signal.
    Type: Application
    Filed: April 9, 2010
    Publication date: October 14, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Takayuki Nakai, Takuma Ishida
  • Patent number: 7795967
    Abstract: There is provided an AGC circuit that has a very small offset voltage and is easy for integration, without using any of external capacities.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Takayuki Nakai, Takuma Ishida
  • Patent number: 7728651
    Abstract: The first control transistor is connected between a first input node for receiving a first input signal swinging between a first voltage and a second voltage and an intermediate node for outputting an output signal, and receives the second voltage at its gate. The second control transistor is connected between a second input node for receiving a second input signal swinging between a third voltage and a fourth voltage in synchronization with the first input signal and the intermediate node, and receives the third voltage at its gate. The voltage difference between the first voltage and the third voltage is smaller than or equal to the source-drain breakdown voltage of the second control transistor, and the voltage difference between the second voltage and the fourth voltage is smaller than or equal to the source-drain breakdown voltage of the first control transistor.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: June 1, 2010
    Assignee: Panasonic Corporation
    Inventor: Takayuki Nakai
  • Publication number: 20090195298
    Abstract: A pumping circuit includes: a pumping capacitance; a first drive transistor connected between an input node for receiving an input voltage and one terminal of the pumping capacitance; and a second drive transistor connected between an output node for outputting an output voltage and the one terminal of the pumping capacitance. In a charge storing mode, the first drive transistor is turned ON to store charge in the pumping capacitance, while in a charge transfer mode, the second drive transistor is turned ON to transfer the charge stored in the pumping capacitance to the output node. The protection circuit puts at least one of the first and second drive transistors in a high-resistance state in which the resistance value is higher than when the transistor is ON, based on whether the output voltage is higher or lower than a predetermined judgment voltage.
    Type: Application
    Filed: November 5, 2008
    Publication date: August 6, 2009
    Inventor: Takayuki NAKAI
  • Publication number: 20090115495
    Abstract: The first control transistor is connected between a first input node for receiving a first input signal swinging between a first voltage and a second voltage and an intermediate node for outputting an output signal, and receives the second voltage at its gate. The second control transistor is connected between a second input node for receiving a second input signal swinging between a third voltage and a fourth voltage in synchronization with the first input signal and the intermediate node, and receives the third voltage at its gate. The voltage difference between the first voltage and the third voltage is smaller than or equal to the source-drain breakdown voltage of the second control transistor, and the voltage difference between the second voltage and the fourth voltage is smaller than or equal to the source-drain breakdown voltage of the first control transistor.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 7, 2009
    Inventor: Takayuki NAKAI
  • Publication number: 20090096528
    Abstract: There is provided an AGC circuit that has a very small offset voltage and is easy for integration, without using any of external capacities.
    Type: Application
    Filed: March 19, 2008
    Publication date: April 16, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Takayuki Nakai, Takuma Ishida
  • Patent number: 5051240
    Abstract: A volatile component detector having a sensor platform fixed inside a main body of a volatile component detector comprises: a sample receptacle which is engagedly supported to a side of a bottom surface of the sensor platform, and the sensor platform has a receptacle support hole which enables a sample receptacle to engage with and be supported in a status of variable and close contact. An odor sensor is set on an inner bottom surface of the receptacle support hole and has its detector portion protruding through the receptacle support hole. The sample receptacle has an opening which enables the insertion of a detector portion of the odor sensor into a top plate. Thus, detector portion of the odor sensor can be inserted into the sample receptacle from the opening when the sample receptacle is engaged with and supported by the receptacle hole of the sensor platform.
    Type: Grant
    Filed: June 1, 1990
    Date of Patent: September 24, 1991
    Assignee: Kirin Beer Kabushiki Kaisha
    Inventors: Takayuki Nakai, Tadahisa Kono