Patents by Inventor Takayuki Nishiura

Takayuki Nishiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080299350
    Abstract: Compound-semiconductor-substrate polishing methods, compound semiconductor substrates, compound-semiconductor-epitaxial-substrate manufacturing methods, and compound semiconductor epitaxial substrates whereby oxygen superficially present on the substrates reduced. A compound semiconductor-substrate polishing method includes a preparation step (S10), a first polishing step (S20), and a second polishing step (S30). In the preparation step (S10), a compound semiconductor substrate is prepared. In the first polishing step (S20), the compound semiconductor substrate is polished with a chloric polishing agent. In the second polishing step (S30), subsequent to the first polishing step (S20), a polishing operation utilizing an alkaline aqueous solution containing an inorganic builder and having pH of 8.5 to 13.0 inclusive is performed.
    Type: Application
    Filed: September 28, 2007
    Publication date: December 4, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshio Mezaki, Takayuki Nishiura, Masahiro Nakayama
  • Publication number: 20080296738
    Abstract: A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle ? by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate.
    Type: Application
    Filed: October 9, 2007
    Publication date: December 4, 2008
    Inventors: Takayuki Nishiura, Yoshio Mezaki, Yusuke Horie, Yasuaki Higuchi
  • Publication number: 20080292877
    Abstract: The present invention provides a method of cleaning a GaAs substrate with less precipitate particles after cleaning. This cleaning method comprises an acid cleaning step (S11), a deionized water rinsing step (S12), and a rotary drying step (S13). First, a GaAs substrate with a mirror finished surface is immersed in an acid cleaning solution in the acid cleaning step (S11). In the acid cleaning step, the cleaning time is less than 30 seconds. Next, the deionized water rinsing step performs the cleaned GaAs substrate with deionized water (S12) to wash away the cleaning solution deposited thereon. Subsequently, the rotary drying step dries the GaAs substrate deposited on deionized water (S13). This provides the cleaned GaAs substrate with less precipitate particles.
    Type: Application
    Filed: April 25, 2005
    Publication date: November 27, 2008
    Inventors: Yusuke Horie, Takayuki Nishiura, Tomoki Uemura
  • Publication number: 20080272392
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Application
    Filed: July 1, 2008
    Publication date: November 6, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Publication number: 20080271667
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Application
    Filed: July 1, 2008
    Publication date: November 6, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Patent number: 7432186
    Abstract: Affords methods of surface treating a substrate and of manufacturing Group III-V compound semiconductors, in which a substrate made of a Group III-V semiconductor compound is rendered stoichiometric, and microscopic roughness on the surface following epitaxial growth is reduced. The methods include preparing a substrate made of a Group III-V semiconductor compound (S10), and cleaning the substrate with a cleaning solution whose pH has been adjusted to an acidity of 2 to 6.3 inclusive, and to which an oxidizing agent has been added (S20).
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: October 7, 2008
    Assignee: Sumitomo Electric Industries, Ltd
    Inventors: Takayuki Nishiura, Tomoki Uemura
  • Patent number: 7416604
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: August 26, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Publication number: 20080176400
    Abstract: Affords a III-V compound semiconductor substrate manufacturing method that enables enhancement of the substrate PL intensity. In such a III-V compound semiconductor substrate manufacturing method, first, the surface 3a of a wafer 3 is polished (polishing step). Second, the surface 3a of the wafer 3 is cleaned (first cleaning step S7). Next, the surface 3a of the wafer 3 is subjected to first dry-etching, employing a halogen-containing gas, while first bias voltage is applied to a chuck 24 for carrying the wafer 3. Subsequently, the surface 3a of the wafer 3 is subjected to second dry-etching, employing the halogen-containing gas (second dry-etching step S11), while second bias power lower than the first bias power is applied to the chuck 24.
    Type: Application
    Filed: January 23, 2008
    Publication date: July 24, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Akihiro Hachigo, Naoki Matsumoto, Takayuki Nishiura
  • Publication number: 20080044338
    Abstract: A method of evaluating damage of a compound semiconductor member, comprising: a step of performing measurement of photoluminescence on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a half width of a peak at a wavelength corresponding to a bandgap of the compound semiconductor member, in an emission spectrum obtained by the measurement of photoluminescence.
    Type: Application
    Filed: October 11, 2007
    Publication date: February 21, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Akihiro Hachigo, Takayuki Nishiura
  • Publication number: 20070281484
    Abstract: A surface treatment method for a nitride crystal is a surface treatment method of chemically and mechanically polishing a surface of the nitride crystal. Oxide abrasive grains are used. The abrasive grains have a standard free energy of formation of at least ?850 kJ/mol as a converted value per 1 mole of oxygen molecules and have a Mohs hardness of at least 4. The surface treatment method efficiently provides, for efficiently obtaining a nitride crystal substrate that can be used for a semiconductor device, the nitride crystal having the smooth and high-quality surface formed thereon.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 6, 2007
    Inventors: Keiji Ishibashi, Takayuki Nishiura, Masato Irikura, Seiji Nakahata
  • Publication number: 20070269989
    Abstract: There are provided an inspection method of a compound semiconductor substrate that can have the amount of impurities at the surface of the compound semiconductor substrate reduced, a compound semiconductor substrate, a surface treatment method of a compound semiconductor substrate, and a method of producing a compound semiconductor crystal. In the inspection method of the surface of the compound semiconductor substrate, the surface roughness Rms of the compound semiconductor substrate is measured using an atomic force microscope at the pitch of not more than 0.4 nm in a scope of not more than 0.2 ?m square. The surface roughness Rms of the compound semiconductor substrate measured by the inspection method is not more than 0.2 nm.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 22, 2007
    Inventors: Takayuki Nishiura, So Tanaka, Yusuke Horie, Kyoko Okita, Takatoshi Okamoto
  • Publication number: 20070254401
    Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.
    Type: Application
    Filed: May 1, 2007
    Publication date: November 1, 2007
    Inventors: Takayuki Nishiura, Keiji Ishibashi
  • Publication number: 20070207630
    Abstract: A surface treatment method of a compound semiconductor substrate, a fabrication method of a compound semiconductor, a compound semiconductor substrate, and a semiconductor wafer are provided, directed to reducing the impurity concentration at a layer formed on a substrate by reducing the impurity concentration at the surface of the substrate formed of a compound semiconductor. The compound semiconductor substrate surface treatment method includes a substrate preparation step and a first washing step. The substrate preparation step includes the step of preparing a substrate formed of a compound semiconductor containing at least 5 mass % of indium. In the first washing step, the substrate is washed for a washing duration of at least 3 seconds and not more than 60 seconds using washing liquid having a pH of at least ?1 and not more than 3, and an oxidation-reduction potential E (mV) satisfying the relationship of ?0.08333x+0.750?E??0.833x+1.333, where x is the pH value.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 6, 2007
    Inventors: Takayuki Nishiura, Kyoko Okita, Yusuke Horie
  • Publication number: 20070080366
    Abstract: A method for working a nitride semiconductor substrate, comprising the steps of: preparing a disk-shaped nitride semiconductor substrate comprising a plurality of striped regions having defect concentration regions in which crystal defect density is higher than in surrounding low defect regions; and forming a cut-out at a specific location along the edge of the nitride semiconductor substrate, using as a reference the direction in which at least one from among the plurality of striped regions extends.
    Type: Application
    Filed: September 7, 2006
    Publication date: April 12, 2007
    Inventors: Takayuki Nishiura, Yoshio Mezaki
  • Publication number: 20070075041
    Abstract: The present polishing slurry is a polishing slurry for chemically mechanically polishing a surface of a GaxIn1-xAsyP1-y crystal (0?x?1, 0?y?1), characterized in that this polishing slurry contains abrasive grains formed of SiO2, this abrasive grain is a secondary particle in which a primary particle is associated, and a ratio d2/d1 of an average particle diameter d2 of a secondary particle to an average particle diameter d1 of a primary particle is not less than 1.6 and not more than 10. According to such the polishing slurry, a crystal surface having a small surface roughness can be formed on a GaxIn1-xAsyP1-y crystal at a high polishing rate and effectively.
    Type: Application
    Filed: September 27, 2006
    Publication date: April 5, 2007
    Inventors: Keiji Ishibashi, Takayuki Nishiura
  • Publication number: 20070023321
    Abstract: The invention relates to a container used to store a compound semiconductor substrate where the content of tin in the container is 1 ppm or less. Further, it relates to a container used to store a compound semiconductor substrate where the content of silicon in the container is 1 ppm or less. Further, it relates to a packaging body used to store a compound semiconductor substrate, where the content of tin in the packaging body is 1 ppm or less. Further, it relates to a manufacturing method of the container and the packaging body and a compound semiconductor substrate stored in the container and the packaging body.
    Type: Application
    Filed: October 3, 2006
    Publication date: February 1, 2007
    Inventors: Noboru Gotou, Takayuki Nishiura, Osamu Ohama
  • Publication number: 20070014915
    Abstract: Affords methods of surface treating a substrate and of manufacturing Group III-V compound semiconductors, in which a substrate made of a Group III-V semiconductor compound is rendered stoichiometric, and microscopic roughness on the surface following epitaxial growth is reduced. The methods include preparing a substrate made of a Group III-V semiconductor compound (S10), and cleaning the substrate with a cleaning solution whose pH has been adjusted to an acidity of 2 to 6.3 inclusive, and to which an oxidizing agent has been added (S20).
    Type: Application
    Filed: June 21, 2006
    Publication date: January 18, 2007
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takayuki Nishiura, Tomoki Uemura
  • Publication number: 20060292832
    Abstract: In a method of working a crystal, when a nitride semiconductor crystal is worked, voltage is applied between the nitride semiconductor crystal and a tool electrode to cause electrical discharge, so that the crystal is partially removed and worked by local heat generated by the electrical discharge.
    Type: Application
    Filed: June 22, 2006
    Publication date: December 28, 2006
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Takayuki Nishiura
  • Publication number: 20060292728
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Application
    Filed: June 23, 2006
    Publication date: December 28, 2006
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Publication number: 20060281201
    Abstract: A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement.
    Type: Application
    Filed: June 13, 2006
    Publication date: December 14, 2006
    Inventors: Akihiro Hachigo, Takayuki Nishiura, Keiji Ishibashi