Abstract: A resist film and a polymer layer adhered on a semiconductor substrate can be removed by the method according to the present invention. A first processing liquid, typically including a oxidizing agent, such as hydrogen peroxide solution, is fed to the substrate, thereby the condition of the resist film and the polymer layer is changed. Next, a second processing liquid, typically including a dimethyl sulfoxide and an amine solvent, is fed to the substrate, thereby the resist film and the polymer layer is dissolved and lifted off from the substrate. A sputtered copper particles included in the polymer layer can also be removed.

Abstract: A resist film and a polymer layer adhered on a semiconductor substrate can be removed by the method according to the present invention. A first processing liquid, typically including a oxidizing agent, such as hydrogen peroxide solution, is fed to the substrate, thereby the condition of the resist film and the polymer layer is changed. Next, a second processing liquid, typically including a dimethyl sulfoxide and an amine solvent, is fed to the substrate, thereby the resist film and the polymer layer is dissolved and lifted off from the substrate. A sputtered copper particles included in the polymer layer can also be removed.

Abstract: A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact region 353 at a surface of a semiconductor substrate 300. The transistor, with the exception of the contact region, is covered with a first material 362, 366 and the first material and the contact region are then covered with a layer of a second material 370. The portion of the second layer covering the contact region is removed to expose the contact region so that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layer 372 in the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layer 376 over the first conductive layer, and forming a second conductive layer 378 over the dielectric layer.

Abstract: The cleaning agent described above comprises a surfactant and an organic solvent, and the cleaning method described above is characterized by allowing the cleaning agent described above to flow on the surface of the material to be treated at a high speed to thereby clean the above surface. According to the present invention, deposits adhering firmly to a surface of a material to be treated can readily be removed without damaging the material to be treated.

Abstract: The present invention is directed to suppressing the rise of a dielectric constant of insulating film during a procedure of burying wiring in semiconductor devices by using a damascene process, and it is also directed to simplifying a process of manufacturing the semiconductor devices. In terms of a process step of forming protection film on a metal layer during the damascene process, there is employed a combined arrangement of a wash unit where particles are removed from polished substrates with a processing unit where a solution containing an organic substance such as benzotriazole, which tends to be bound to the metal layers, is applied to the metal layers over the substrates after the particles are removed therefrom. For the combined arrangement of the processing unit and the wash unit, either a batch processing unit or a mono/serial processing unit can be employed.

Abstract: An embodiment of the instant invention is a method of oxidizing a first feature (feature 108 and/or feature 104 of FIG. 1 and feature 314 of FIG. 3) while leaving a second feature substantially unoxidized (features 110 and 112 of FIG. 1 and features 310 and 312 of FIG. 3), the method comprised of subjecting the first and second features to an oxygen-containing gas and a separate hydrogen-containing gas. Preferably, the oxygen-containing gas is comprised of gas selected from the group consisting of O2, N2O, CO2, H2O, and any combination thereof, and the hydrogen-containing gas is comprised of H2. The first feature is, preferably, comprised of polycrystalline silicon, silicon oxide, or a dielectric material, and the second feature is, preferably, comprised of tungsten.

Abstract: A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact region 353 at a surface of a semiconductor substrate 300. The transistor, with the exception of the contact region, is covered with a first material 362, 366 and the first material and the contact region are then covered with a layer of a second material 370. The portion of the second layer covering the contact region is removed to expose the contact region so that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layer 372 in the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layer 376 over the first conductive layer, and forming a second conductive layer 378 over the dielectric layer.

Abstract: A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact region 353 at a surface of a semiconductor substrate 300. The transistor, with the exception of the contact region, is covered with a first material 362, 366 and the first material and the contact region are then covered with a layer of a second material 370. The portion of the second layer covering the contact region is removed to expose the contact region so that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layer 372 in the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layer 376 over the first conductive layer, and forming a second conductive layer 378 over the dielectric layer.

Abstract: The object of the present invention is to provide a plating method capable of planarization process of high quality in comparison with the conventional plating method and also provide a plating device and a plating system adopting the plating method of the invention. In the plating method and device, an object 10 to be processed and an electrode plate 20 are dipped in a solution including objective metal ions and a forward current is supplied between the object and the electrode plate to educe a metal on the surface of the object. After forming a plating film on the object excessively, a backward current is supplied between the object 10 and the electrode 20 to uniformly remove at least part of superfluous plating film.

Abstract: A resist film and a polymer layer adhered on a semiconductor substrate can be removed by the method according to the present invention. A first processing liquid, typically including a oxidizing agent, such as hydrogen peroxide solution, is fed to the substrate, thereby the condition of the resist film and the polymer layer is changed. Next, a second processing liquid, typically including a dimethyl sulfoxide and an amine solvent, is fed to the substrate, thereby the resist film and the polymer layer is dissolved and lifted off from the substrate. A sputtered copper particles included in the polymer layer can also be removed.

Abstract: The cleaning method described above is characterized by allowing a cleaning agent comprising an oxidizing agent, a chelating agent and fluorine compound to flow on a surface of a material to be treated at a high speed to thereby clean the above surface according to the present invention, deposits adhering firmly to a surface of a material to be treated can readily be removed without damaging the material to be treated.

Abstract: There is provided a cleaning device capable of preventing a metal wiring layer or the like of an object to be treated, from being oxidized. The cleaning device comprises: a cleaning container 72 having a treating space S having a slightly larger volume than that of an object W to be treated; a fluid storage tank 30 for storing a cleaning fluid 32 for treating the object; supply lines 46A through 46D for supplying the cleaning fluid from the fluid storage tank to the cleaning container; and reflux lines 47A through 47D for returning the cleaning fluid from the cleaning container to the fluid storage tank, wherein the cleaning container, the fluid storage tank, the supply lines and the reflux lines are associated with each other for forming closed cleaning fluid circulating lines 51A through 51D. Thus, it is possible to prevent the metal wiring layer or the like of the object from being oxidized.

Abstract: A structure and method for fabricating an integrate circuit crown structure for use in a DRAM cell on a substrate comprising a common source/drain region (18) disposed within a substrate (12), the common source/drain region (18) connected to a bitline (22), a gate oxide (28) disposed over the common source/drain region (18) and forming at least two wordline gates (30), at least two storage node source/drains (20) adjacent to said gates (30) and contacted by storage node contacts (38) and a storage node bowl (36), the bowl being formed within adjacent supporting layers formed over said wordline gates wherein the storage node bowl (36) is formed, and electrically isolated from, the bitline (22) without being exposed to etching agents during its formation and without forming a wine glass stem structure and a crown extending from the top of the storage node bowl (36), is disclosed.

Abstract: The cleaning method described above is characterized by allowing a cleaning agent comprising an oxidizing agent, a chelating agent and a fluorine compound to flow on a surface of a material to be treated at a bigh speed to thereby clean the above surface. according to the present invention, deposits adhering firmly to a surface of a material to be treated can readily be removed without damaging the material to be treated.

Abstract: The cleaning agent described above comprises a surfactant and an organic solvent, and the cleaning method described above is characterized by allowing the cleaning agent described above to flow on the surface of the material to be treated at a high speed to thereby clean the above surface. According to the present invention, deposits adhering firmly to a surface of a material to be treated can readily be removed without damaging the material to be treated.

Abstract: A structure and method for fabricating an integrated circuit crown structure for use in a DRAM cell on a substrate comprising a common source/drain region (18) disposed within a substrate (12), the common source/drain region (18) connected to a bitline (22), a gate oxide (28) disposed over the common source/drain region (18) and forming at least two wordline gates (30), at least two storage node source/drains (20) adjacent to said gates (30) and contacted by storage node contacts (38) and a storage node bowl (36), the bowl being formed within adjacent supporting layers formed over said wordline gates wherein the storage node bowl (36) is formed, and electrically isolated from, the bitline (22) without being exposed to etching agents during its formation and without forming a wine glass stem structure and a crown extending from the top of the storage node bowl (36), is disclosed.

Abstract: A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (14) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (46, 52, 54) are disposed. A silicon nitride layer (30) is in place below the BPSG layer (14), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (14) during high temperature processes such as reflow and densification of the BPSG layer (14) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (14) and the silicon nitride layer (30) using a two-step etch process.

Abstract: A method for fabricating a memory cell includes forming a first access line (16) for a storage node (140, 210) and forming a second access line (82) operable to access the storage node (140, 210) in connection with the first access line (16). The first access line (16) includes a first terminal (32) and a second terminal (34). The second access line (82) includes a conductive layer (70) connected to the first terminal (32) of the first access line (16). An opening (88) is formed in the second access line (82) for connection of the storage node (140, 210) to the second terminal (34) of the first access line (16). A sidewall (92) is formed in the opening (88) to form a contact hole (94) insulated from the conductor (70) of the second access line (82). The storage node (140, 210) is formed having a self-aligned contact (102) formed in the contact hole (94) and connected to the second terminal (34) of the first access line (16).

Abstract: A cleaning agent for use in producing semiconductor devices. The cleaning agent is an aqueous solution containing (A) a fluorine-containing compound, (B) a salt of boric acid, (C) a water-soluble organic solvent, and optionally, (D) a specific quaternary ammonium salt or (D′) a specific ammonium salt of an organic carboxylic acid or a specific amine salt of an organic carboxylic acid. The polymeric deposit inside and around the via holes and on the side wall of the conductive line pattern formed during the dry etching process can be effectively removed by using the cleaning agent without affecting the dimensions of the via holes and the conductive line pattern.

Abstract: A semiconductor device (2) includes gates (20, 22, 24, 26), source/drain regions (40, 42, 44, 46), and self-aligned contacts (80, 82, 84, 86). Each self-aligned contact (80, 82, 84, 86) includes a polysilicon layer (50) overlying the associated source/drain region (40, 42, 44, 46). The polysilicon layer (50) may include different doped regions (52, 58) in accordance with the design and function of the device (2).