Abstract: To provide a semiconductor apparatus including a transistor element layer having a plurality of transistors which are multi-gate transistors of a floating body structure, a first wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors, the first wiring layer being laminated on the side of one surface of the transistor element layer, and a second wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors, the second wiring layer being laminated on the side of another surface of the transistor element layer.

Abstract: A stacked chip is provided comprising a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip has a first supporting substrate and a first circuit layer including a first region in which a first circuit is formed and a second region in which a second circuit is formed, the second semiconductor chip has a second supporting substrate, a second circuit layer including a third region that corresponds to a position of the first region and a fourth region that corresponds to a position of the second region and in which the second circuit is formed, a first embedded portion embedded in a first hole portion penetrating through the third region and extending to an inside of the second supporting substrate, and a first through via that penetrates through the first embedded portion and the second supporting substrate, and is electrically conducted with the first circuit.

Abstract: A light emitting sealed body includes: a housing which stores a discharge gas and is provided with a first opening to which first light is incident along a first optical axis and a second opening from which second light is emitted along a second optical axis; a first window portion which hermetically seals the first opening; and a second window portion which hermetically seals the second opening. The housing is formed of a light shielding material which does not transmit the first light and the second light. An internal space is defined by the housing, the first window portion, and the second window portion and the internal space is filled with the discharge gas. The first opening and the second opening are disposed so that the first optical axis and the second optical axis intersect each other.

Abstract: A method for manufacturing a semiconductor device is provided. In the method, first substrate is prepared. Each of the first substrates has first product regions. The first substrates are stacked, thereby electrically connecting different layers of the first substrates via a through-electrode. A second substrates having second product regions is prepared. Second semiconductor chips are attached to the second product regions. The second semiconductor chips are attached to the second substrate on a top layer of the first substrates. The second substrate is removed from the second semiconductor chips. First electrode pads of the top layer are electrically connected to second electrode pads of the second semiconductor chips via through-electrodes. The second semiconductor chips are connected to each other in parallel. The first and second product regions are separated, thereby manufacturing semiconductor chip stacks including more semiconductor chips in the top layer than the other layers.

Abstract: Provided is a stacked device comprising: a plurality of circuit layers each having a circuit portion; an insulating layer configured to cover a plurality of circuit portions included in a part of circuit layers of the plurality of circuit layers, and a plurality of conductive vias provided in the insulating layer and electrically connected to the plurality of circuit portions, wherein the conductive via electrically connected to a partial circuit portion of the plurality of circuit portions is electrically insulated on an end surface on an opposite side to the plurality of circuit portions and the partial circuit portion is broken at least partially along a stacking direction.

Abstract: A semiconductor device includes a power supply and ground layer and a semiconductor chip disposed over the power supply and ground layer. The power supply and ground layer includes a substrate and a wiring part. The substrate has one or more grooves whose openings are directed toward the semiconductor chip, and the wiring part is disposed within the one or more grooves via an insulating layer and is formed in a predetermined pattern. The substrate is connected to ground wiring of the semiconductor chip and the wiring part is connected to power supply wiring of the semiconductor chip. The wiring part is not exposed from a back surface of the substrate.

Abstract: A semiconductor device according to the present invention is formed by a plurality of semiconductor chips laminated on a substrate which are connected via a through electrode penetrating in a lamination direction, in which the plurality of semiconductor chips include first semiconductor chips 104 each having memory blocks and a decoder and a second semiconductor chip having a logic circuit, the logic circuit includes one selection circuit connected to the decoder of all the first semiconductor chips 104 and configured to select addresses of a first memory block 106A that stops input/output and a second memory block 106B that performs input/output instead among the plurality of memory blocks, and the addresses of the selected first memory block 106A and the selected second memory block 106B are each common to all the first semiconductor chips.

Abstract: This semiconductor device includes a memory semiconductor chip having a plurality of memory cells, a planar buffer chip which is a semiconductor chip that comprises a plurality of buffer circuits which hold data read from the memory cell and data written to the memory cell and which output the held data in accordance with the number of bit lines of the plurality of memory cells, an electrical connection structure which electrically connects the bit lines of the memory cells of the memory semiconductor chip and the buffer circuits of the planar buffer chip to each other in a thickness direction of the memory semiconductor chip and the planar buffer chip, and a plurality of bit wiring layers provided in accordance with the respective buffer circuits and electrically connected to the bit lines of the buffer circuits. The bit wiring layers are laminated on the planar buffer chip.

Abstract: This semiconductor device includes a memory semiconductor chip in which a plurality of memory cells are laminated on a semiconductor substrate, a planar buffer chip which is a semiconductor chip that comprises a plurality of buffer circuits which hold data read from the memory cell and data written to the memory cell and which output the held data in accordance with the number of bit lines of the plurality of memory cells, and an electrical connection structure which electrically connects the bit lines of the memory cells of the memory semiconductor chips and the buffer circuits of the planar buffer chips to each other in a thickness direction of the memory semiconductor chip and the planar buffer chip. The electrical connection structure electrically connects the bit lines of the plurality of memory cells in the thickness direction through a penetration electrode penetrating at least the plurality of memory cells in the thickness direction.

Abstract: A first substrate having a first face and a second face is prepared. The first face has a plurality of product regions defined thereon. An electrode pad forming side of each of a semiconductor chip stack and a semiconductor chip is attached to each corresponding product region of the plurality of product regions. The second face of the first substrate is thinned. A first inorganic insulating layer is formed on the second face. A first vertical interconnection penetrates the first inorganic insulating layer and the first substrate and is electrically connected to an electrode pad of the semiconductor chip stack. A second vertical interconnection penetrates the first inorganic insulating layer and the first substrate and is electrically connected to an electrode pad of the semiconductor chip. A first horizontal interconnection electrically connects a part of the first vertical interconnection to a part of the second vertical interconnection.

Abstract: A method for manufacturing a semiconductor device is provided. In the method, first substrate is prepared. Each of the first substrates has first product regions. The first substrates are stacked, thereby electrically connecting different layers of the first substrates via a through-electrode. A second substrates having second product regions is prepared. Second semiconductor chips are attached to the second product regions. The second semiconductor chips are attached to the second substrate on a top layer of the first substrates. The second substrate is removed from the second semiconductor chips. First electrode pads of the top layer are electrically connected to second electrode pads of the second semiconductor chips via through-electrodes. The second semiconductor chips are connected to each other in parallel. The first and second product regions are separated, thereby manufacturing semiconductor chip stacks including more semiconductor chips in the top layer than the other layers.

Abstract: A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; and a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips, wherein a semiconductor chip has at least one sub-memory array, and a penetration electrode penetrates through an outer circumferential part of the sub-memory array.

Abstract: A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips; and a plurality of input/output elements that are configured to perform a signal input/output operation to the plurality of penetration electrodes, wherein the semiconductor chips are joined together via no bump, one of the plurality of input/output elements is connected to each of the plurality of penetration electrodes such that a functional element connected to each of the plurality of penetration electrodes performs an ON or OFF operation at a predetermined timing, and the input/output element connected to a first of two adjacent penetration electrodes among the plurality of penetration electrodes and the input/output element connected to a second of two adjacent pene

Abstract: A semiconductor device according to the present invention is formed by a plurality of semiconductor chips laminated on a substrate which are connected via a through electrode penetrating in a lamination direction, in which the plurality of semiconductor chips include first semiconductor chips 104 each having memory blocks and a decoder and a second semiconductor chip having a logic circuit, the logic circuit includes one selection circuit connected to the decoder of all the first semiconductor chips 104 and configured to select addresses of a first memory block 106A that stops input/output and a second memory block 106B that performs input/output instead among the plurality of memory blocks, and the addresses of the selected first memory block 106A and the selected second memory block 106B are each common to all the first semiconductor chips.

Abstract: This semiconductor device includes a memory semiconductor chip in which a plurality of memory cells are laminated on a semiconductor substrate, a planar buffer chip which is a semiconductor chip that comprises a plurality of buffer circuits which hold data read from the memory cell and data written to the memory cell and which output the held data in accordance with the number of bit lines of the plurality of memory cells, and an electrical connection structure which electrically connects the bit lines of the memory cells of the memory semiconductor chips and the buffer circuits of the planar buffer chips to each other in a thickness direction of the memory semiconductor chip and the planar buffer chip. The electrical connection structure electrically connects the bit lines of the plurality of memory cells in the thickness direction through a penetration electrode penetrating at least the plurality of memory cells in the thickness direction.

Abstract: This semiconductor device includes a memory semiconductor chip having a plurality of memory cells, a planar buffer chip which is a semiconductor chip that comprises a plurality of buffer circuits which hold data read from the memory cell and data written to the memory cell and which output the held data in accordance with the number of bit lines of the plurality of memory cells, an electrical connection structure which electrically connects the bit lines of the memory cells of the memory semiconductor chip and the buffer circuits of the planar buffer chip to each other in a thickness direction of the memory semiconductor chip and the planar buffer chip, and a plurality of bit wiring layers provided in accordance with the respective buffer circuits and electrically connected to the bit lines of the buffer circuits. The bit wiring layers are laminated on the planar buffer chip.

Abstract: When testing a memory chip, the memory chip is determined to be defective if even a portion of the memory chip is defective, and is discarded, which lowers the yield of the three-dimensional memory device. A three-dimensional device is provided comprising a plurality of stacked circuit chips each having one or more circuit blocks in each of a plurality of divided regions obtained by dividing a circuit plane and an interconnect portion communicatively connected, for each group of circuit blocks included in each of the divided regions overlapping in a stacking direction in the plurality of circuit chips, to a predetermined number of circuit blocks sorted from the circuit blocks within the group.

Abstract: A semiconductor apparatus includes a chip laminate body in which a plurality of memory chips are laminated on a logic chip that controls each of the plurality of memory chips, wherein the chip laminate body includes a plurality of penetration electrodes that penetrate through the plurality of memory chips and the logic chip in a thickness direction and includes a bumpless structure in which the plurality of memory chips and the logic chip are electrically connected together via the plurality of penetration electrodes without arranging a bump electrode in each space among the plurality of memory chips and the logic chip, and a conductance of a first transistor provided on the plurality of memory chips is smaller than a conductance of a second transistor provided on the logic chip.

Abstract: A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips; and a plurality of input/output elements that are configured to perform a signal input/output operation to the plurality of penetration electrodes, wherein the semiconductor chips are joined together via no bump, one of the plurality of input/output elements is connected to each of the plurality of penetration electrodes such that a functional element connected to each of the plurality of penetration electrodes performs an ON or OFF operation at a predetermined timing, and the input/output element connected to a first of two adjacent penetration electrodes among the plurality of penetration electrodes and the input/output element connected to a second of two adjacent pene

Abstract: A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; and a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips, wherein a semiconductor chip has at least one sub-memory array, and a penetration electrode penetrates through an outer circumferential part of the sub-memory array.