Abstract: A technique for enhancing reliability is provided. A semiconductor device includes a main device which operates in a delayed lockstep mode, a sub device which operates in parallel to the main device in a delayed lockstep mode, a delay circuit which delays an output of the main device, a switching circuit which switches the main device to the sub device according to failure information of the main device.

Abstract: When one of CPUs that perform a lock step operation fails and the failure type is an SW failure, the semiconductor device copies information held by an SR and a GR of the CPU operating normally to the CPU with the SW failure, thereby continuing a process without stopping the lock step operation. On the other hand, when the failure type is an HW failure, the failed CPU is stopped to continue the process with only the normal CPU.

Abstract: To provide a conductive member for an electrophotographic machine that is capable of preventing hardening degradation of a surface layer that is caused by an ionic conductive agent contained in a conductive rubber elastic body layer, allowing the surface layer to be improved in durability. A conductive member 10 for an electrophotographic machine includes a conductive rubber elastic body layer 14 containing crosslinked rubber and an ionic conductive agent, and a surface layer 16 provided on an outer periphery of the conductive rubber elastic body layer 14, wherein the surface layer 16 contains a polymer and polyphenol. Examples of the polyphenol include a tannin, gallic acid, ellagic acid, pyrogallol, catechin, and chlorogenic acid.

Abstract: To provide a conductive member for an electrophotographic machine that is capable of preventing hardening degradation of a surface layer that is caused by an ionic conductive agent contained in a conductive rubber elastic body layer, allowing the surface layer to be improved in durability. A conductive member 10 for an electrophotographic machine includes a conductive rubber elastic body layer 14 containing crossiinked rubber and an ionic conductive agent, and a surface layer 16 provided on an outer periphery of the conductive rubber elastic body layer 14, wherein the surface layer 16 contains a polymer and polyphenol. Examples of the polyphenol include a tannin, gallic acid, ellagic acid, pyrogallol, catechin, and chlorogenic acid.

Abstract: A bus circuit which transfers data of a plurality of bits output from one module to another module, includes: a data bus; a division circuit configured to divide the data into a plurality of pieces of divided data including a plurality of bits in a number equal to or less than half a bit width of the data bus; an inverter circuit configured to generate a plurality of pieces of inverted divided data by inverting each of the plurality of pieces of divided data; an output circuit configured to output each of the plurality of pieces of divided data and each of the pieces of inverted divided data corresponding to each of the pieces of divided data as a data pair; and a coupling circuit configured to extract and couple the plurality of pieces of divided data from the data pair received from the data bus.

Abstract: A flush toilet stool includes a toilet bowl and a trap drainage passage connected to the toilet bowl. The toilet bowl has a water jet hole defined in a bottom region thereof and opening toward the trap drainage passage. A pressurizing unit such as a water pump is coupled to the water jet hole for drawing water under lower pressure directly from an external water supply and expelling the water under higher pressure through the water jet hole toward the trap drainage passage to develop a siphon flow to discharge sewage from the toilet bowl through the trap drainage passage.

Abstract: There is disclosed a semiconductor memory device comprising a plurality of blocks in which memory cells are respectively arranged on a plurality of normal rows and one spare row. Each block includes a plurality of normal row selection lines for selecting any one of the normal rows, and one spare row selection line for instead selecting the spare row in the case where any one of the normal rows is defective. The device further comprises non-selection circuit elements provided for every normal row selection line, and being such that when a corresponding normal row is defective, the non-selection circuit element allows that defective normal row selection line to be brought into non-selective state; and a selector adapted so that when the normal rows in a corresponding block are all in non-selective state, the selector allows the spare row selection line to be brought into selective state. Also, with respect to a column direction, a circuit configuration similar to the above may be provided.

Abstract: A sense amplifier circuit characterized by comprising differential amplifying means for amplifying and outputting supplied differential input signals, and bias current control means, connected between the differential amplifying means and a ground voltage, for controlling an amount of bias current in response to the output of the differential amplifying means.

Abstract: A semiconductor integrated circuit equipped with an input buffer operation error preventing circuit is disclosed. A semiconductor integrated circuit comprises a data output signal level detector circuit for detecting at least one of a variation from a low level to a high level and that from a high level to a low level of a signal outputted from a circuit of a stage preceding an output buffer and for generating a clock pulse and an input buffer threshold level control circuit for controllably varying the threshold level of a first-stage gate in an input buffer by inputting the clock pulse so as to cancel a fall in an input level detection margin of the input buffer which is caused when the output data of the output buffer varies from a "0" level to a "1" level and vice versa.

Abstract: A semiconductor integrated circuit equipped with an input buffer operation error prevention circuit is disclosed which comprises a data output signal level transition detector circuit for detecting at least one of a variation from a low level from a high level and a variation from a high level to a low level of a signal of a circuit of a stage preceding an output buffer and for generating a clock pulse and an input buffer signal terminal control circuit for controlling the terminal level of a first stage gate in an input buffer through the use of a clock pulse so as to cancel a fall in an input level detection margin of the input buffer which is caused when the output data of the output buffer varies from a "0" level to a "1" level and vice versa.

Abstract: A semiconductor memory device includes a control circuit for disabling a bit-line load circuit coupled to a column of memory cells in a static RAM only when a write enable signal and a column select signal are applied to the column.

Abstract: A row address signal is supplied to a row address input buffer, and a column address signal is supplied to a column address input buffer. The row address signal supplied to the row address input buffer is then supplied to a row main decoder, through a row address predecoder, the column address signal supplied to the column address input buffer being supplied to a column address predecoder. An output from the column address predecoder is supplied to a filter or delay circuit, and an output signal from the filter or delay circuit is supplied to a column main decoder. One memory cell in a memory cell array is selected in response to decode outputs from the row main decoder and the column main decoder, and readout data of the selected memory cell is amplified by a sense amplifier. An output from the sense amplifier is output through a data output circuit and a data output buffer.

Abstract: A static semiconductor memory comprises a word line, a memory cell array divided into a plurality of blocks in an extending direction of the word line, each block including a plurality of sections each of which includes a plurality of static memory cells, a controller, a section data line provided for each section, first sense amplifiers, a block data line provided for each block, second sense amplifiers, a main data line and a latch circuit for latching data on the main data line. The controller selects an arbitrary section in the memory cell array at the time of data readout and controls the reading of data from memory cells included in the selected section. The section data line is supplied with data read out from the memory cells. The first sense amplifiers, coupled at their input terminals to the section data line, are activated only when their associated section is selected. The individual first sense amplifiers in the same block have their output terminals commonly coupled to the block data line.

Abstract: A semiconductor memory device comprising a memory cell-selecting section, an input supply control section, and a bit-line potential control section. The memory cell-selecting section includes a row decoder and a first gate circuit coupled to the output thereof. The memory cell-selecting section drives all the memory cells making up the memory device, when it is set in the mode for clearing the memory device, and the input data supply control section disconnects a pair of bit lines from a write circuit when the control section is set in this same mode. When the bit-line potential control section is set in the memory-clearing mode, it sets the potential of one of the bit lines at a high level, and the potential of the other bit line at a low potential.