Abstract: A semiconductor device includes a semiconductor substrate that includes a drift layer, a drain layer, a first well region and a second well region in the drift layer, a first source region selectively formed in the first well region, and a second source region selectively formed in the second well region; a gate insulating film selectively disposed on the semiconductor substrate and covering a portion of the drift layer sandwiched by the first well region and the second well region, the gate insulating film including a first portion and a second portion thicker than the first portion, arranged side by side so as to be laterally continuous to each other, the first portion being arranged on the first well region, the second portion being arranged on the second well region; and a gate electrode disposed on the gate insulating film that includes the first and second portions.

Abstract: Provided is a semiconductor device including a semiconductor chip; a frame member having a chip placement surface on which the semiconductor chip is provided; and a first suspension lead and a second suspension lead connected to the frame member and provided on any side of the frame member, wherein M1?L1+L2 is satisfied, where L1 is a distance from an arrangement position of the first suspension lead to a corner of the chip placement surface close to the first suspension lead, L2 is a distance from an arrangement position of the second suspension lead to a corner of the chip placement surface close to the second suspension lead, and M1 is a distance from the arrangement position of the first suspension lead to the arrangement position of the second suspension lead.

Abstract: To provide a semiconductor package including a protruding part at the bottom surface of a package main body. A semiconductor package including a semiconductor chip is provided, the semiconductor package including: a package main body; a plurality of electrodes exposed at a bottom surface of the package main body; and a protruding part projecting from the bottom surface of the package main body and above the plurality of electrodes, wherein the protruding part is arranged not to overlap two least separated electrodes, among the plurality of electrodes, in a second direction different from a first direction in which the two electrodes are arrayed.

Abstract: To easily assess a feedback capacitance of a semiconductor element. An assessment method of assessing a feedback capacitance of a semiconductor element is provided, the assessment method including: acquiring a first characteristic correlated with the feedback capacitance and a second characteristic correlated with the feedback capacitance; and assessing the feedback capacitance based on the first characteristic and the second characteristic. The first characteristic may be a characteristic that corresponds to a withstanding voltage of the semiconductor element, and the second characteristic may be an on-resistance of the semiconductor element. In the assessing, the feedback capacitance may be assessed based on a ratio between the first characteristic and the second characteristic.

Abstract: To easily assess a feedback capacitance of a semiconductor element. An assessment method of assessing a feedback capacitance of a semiconductor element is provided, the assessment method including: acquiring a first characteristic correlated with the feedback capacitance and a second characteristic correlated with the feedback capacitance; and assessing the feedback capacitance based on the first characteristic and the second characteristic. The first characteristic may be a characteristic that corresponds to a withstanding voltage of the semiconductor element, and the second characteristic may be an on-resistance of the semiconductor element. In the assessing, the feedback capacitance may be assessed based on a ratio between the first characteristic and the second characteristic.

Abstract: Provided is a semiconductor device including a semiconductor chip; a frame member having a chip placement surface on which the semiconductor chip is provided; and a first suspension lead and a second suspension lead connected to the frame member and provided on any side of the frame member, wherein M1?L1+L2 is satisfied, where L1 is a distance from an arrangement position of the first suspension lead to a corner of the chip placement surface close to the first suspension lead, L2 is a distance from an arrangement position of the second suspension lead to a corner of the chip placement surface close to the second suspension lead, and M1 is a distance from the arrangement position of the first suspension lead to the arrangement position of the second suspension lead.

Abstract: To easily assess a feedback capacitance of a semiconductor element. An assessment method of assessing a feedback capacitance of a semiconductor element is provided, the assessment method including: acquiring a first characteristic correlated with the feedback capacitance and a second characteristic correlated with the feedback capacitance; and assessing the feedback capacitance based on the first characteristic and the second characteristic. The first characteristic may be a characteristic that corresponds to a withstanding voltage of the semiconductor element, and the second characteristic may be an on-resistance of the semiconductor element. In the assessing, the feedback capacitance may be assessed based on a ratio between the first characteristic and the second characteristic.

Abstract: To provide a semiconductor package including a protruding part at the bottom surface of a package main body. A semiconductor package including a semiconductor chip is provided, the semiconductor package including: a package main body; a plurality of electrodes exposed at a bottom surface of the package main body; and a protruding part projecting from the bottom surface of the package main body and above the plurality of electrodes, wherein the protruding part is arranged not to overlap two least separated electrodes, among the plurality of electrodes, in a second direction different from a first direction in which the two electrodes are arrayed.

Abstract: To easily assess a feedback capacitance of a semiconductor element. An assessment method of assessing a feedback capacitance of a semiconductor element is provided, the assessment method including: acquiring a first characteristic correlated with the feedback capacitance and a second characteristic correlated with the feedback capacitance; and assessing the feedback capacitance based on the first characteristic and the second characteristic. The first characteristic may be a characteristic that corresponds to a withstanding voltage of the semiconductor element, and the second characteristic may be an on-resistance of the semiconductor element. In the assessing, the feedback capacitance may be assessed based on a ratio between the first characteristic and the second characteristic.

Abstract: A gate pad electrode and a source electrode are disposed, separately from one another, on the front surface of a super junction semiconductor substrate. A MOS gate structure formed of n source regions, p channel regions, p contact regions, a gate oxide film, and polysilicon gate electrodes is formed immediately below the source electrode. The p well regions are formed immediately below the gate pad electrode. The p channel regions are linked to the p well regions via extension portions. By making the width of the p well regions wider than the width of the p channel regions, it is possible to reduce a voltage drop caused by a reverse recovery current generated in a reverse recovery process of a body diode.

Abstract: A gate pad electrode and a source electrode are disposed, separately from one another, on the front surface of a super junction semiconductor substrate. A MOS gate structure formed of n source regions, p channel regions, p contact regions, a gate oxide film, and polysilicon gate electrodes is formed immediately below the source electrode. The p well regions are formed immediately below the gate pad electrode. The p channel regions are linked to the p well regions via extension portions. By making the width of the p well regions wider than the width of the p channel regions, it is possible to reduce a voltage drop caused by a reverse recovery current generated in a reverse recovery process of a body diode.

Abstract: A semiconductor device includes element active portion X and element peripheral portion Y. An interlayer insulating film is formed on upper surfaces of portions X and Y. A source electrode connected to a p base region and n-type source region and a gate metal wiring formed annularly surrounding the source electrode are formed on element active portion X side upper surface of the interlayer insulating film. The gate metal wiring connects to a gate electrode. An organic protective film with openings is formed on a first main surface side upper surface of the semiconductor substrate, and the openings serve as a gate electrode pad partially exposing the gate metal wiring and a source electrode pad partially exposing the source electrode. An inorganic protective film formed between the gate metal wiring and the organic protective film covers the gate metal wiring. The semiconductor device is highly reliable.

Abstract: A semiconductor device includes element active portion X and element peripheral portion Y. An interlayer insulating film is formed on upper surfaces of portions X and Y. A source electrode connected to a p base region and n-type source region and a gate metal wiring formed annularly surrounding the source electrode are formed on element active portion X side upper surface of the interlayer insulating film. The gate metal wiring connects to a gate electrode. An organic protective film with openings is formed on a first main surface side upper surface of the semiconductor substrate, and the openings serve as a gate electrode pad partially exposing the gate metal wiring and a source electrode pad partially exposing the source electrode. An inorganic protective film formed between the gate metal wiring and the organic protective film covers the gate metal wiring. The semiconductor device is highly reliable.

Abstract: A method of manufacturing a super-junction semiconductor device includes growing an alternating conductivity type layer epitaxially on a heavily doped n-type semiconductor substrate, the alternating conductivity type layer including n-type and p-type semiconductor regions arranged alternately and repeated such that n-type and p-type regions are adjoining each other, and arranged to extend perpendicular to the substrate's major surface. The method includes forming a first trench having a predetermined depth in the surface portion of n-type semiconductor region; forming an n-type thin layer on the inner surface of the first trench; and burying gate electrode in the space surrounded by the n-type thin layer with a gate insulator film interposed between a gate electrode and the n-type thin layer.

Abstract: A method of manufacturing a super-junction semiconductor device prevents mutual positional deviation between the region of the first conductivity type in the alternating conductivity type layer and the second trench for forming a trench gate from resulting. The method includes growing an alternating conductivity type layer epitaxially on a heavily doped n-type semiconductor substrate, the alternating conductivity type layer including n-type and p-type semiconductor regions arranged alternately and repeated such that n-type and p-type regions are adjoining each other, and arranged to extend perpendicular to the substrate's major surface.