Abstract: An information processing apparatus switches a clock to reduce power consumption of an information processing unit. In order to reduce an overhead time in switching, the information processing apparatus includes an interrupt controller for generating a clock switch signal by accepting an interrupt to each information processing unit and a clock switch circuit for switching the clock to be supplied to the information processing unit. Using a hardware interrupt signal to switch the clock to be supplied to circuits, the circuit clock can be switched real time, and reduction of the power consumption can be achieved.

Abstract: An information processing apparatus switches a clock to reduce power consumption of an information processing unit. In order to reduce an overhead time in switching, the information processing apparatus includes an interrupt controller for generating a clock switch signal by accepting an interrupt to each information processing unit and a clock switch circuit for switching the clock to be supplied to the information processing unit. Using a hardware interrupt signal to switch the clock to be supplied to circuits, the circuit clock can be switched real time, and reduction of the power consumption can be achieved.

Abstract: In a data processing device, a processor processes data based on a stored program and a buffer manager accesses the data. The data processing device includes a program memory which stores program codes, the program codes being loaded into the program memory and executed by the processor when processing the data. A shared memory stores one of the program codes and the data. A control unit selectively connects one of the processor and the buffer manager to the shared memory based on a select pattern, wherein the shared memory functions to store the program codes when the select pattern is set in a first condition, and the shared memory functions to store the data when the select pattern is set in a second condition.

Abstract: In a data processing device, a processor processes data based on a stored program and a buffer manager accesses the data. The data processing device includes a program memory which stores program codes, the program codes being loaded into the program memory and executed by the processor when processing the data. A shared memory stores one of the program codes and the data. A control unit selectively connects one of the processor and the buffer manager to the shared memory based on a select pattern, wherein the shared memory functions to store the program codes when the select pattern is set in a first condition, and the shared memory functions to store the data when the select pattern is set in a second condition.