Abstract: A semiconductor memory device includes of a plurality of sense amplifiers. The sense amplifiers are arranged in two amplifier columns. The two amplifier columns are disposed between two cell columns of cell plates. An address circuitry, an ATD circuitry, and a delay circuitry are disposed between an input pin row and the two cell columns. An ATD pulse synthesizer is disposed between the two amplifier columns and spaced a predetermined signal transmission path from the ATD and delay circuitries.

Abstract: A semiconductor memory device is comprised of a plurality of sense amplifiers. The sense amplifiers are arranged in two amplifier columns. The two amplifier columns are disposed between two cell columns of cell plates. An address circuitry, an ATD circuitry, and a delay circuitry are disposed between an input pin row and the two cell columns. An ATD pulse synthesizer Is disposed between the two amplifier columns and spaced a predetermined signal transmission path from the ATD and delay circuitries.

Abstract: A voltage generation circuit for a multivalued cell type mask ROM includes partial circuits of the same number as the row number of memory cell transistors. Each of the partial circuits includes a cell part circuit, which includes a memory cell transistor and a resistor, which is formed to have the same resistance as the resistance parasitically added to a source and a drain of a memory cell transistor. Each of the partial circuits is supplied with the same signal as the signal supplied to a corresponding word line, so that the partial circuit corresponding to the word line of a selected memory cell transistor is selected to generate a voltage interlocked with a variation in the threshold caused by a difference between the source potential and the substrate potential.

Abstract: A voltage generator circuit includes a loading transistor circuit having a source terminal supplied with a power source voltage, a transfer gate circuit having a source terminal connected with the drain terminal of the loading transistor circuit, a clamping circuit having a drain terminal connected with the drain terminal of the transfer gate circuit and a source terminal which is grounded, and an inverter circuit which is provided between the drain terminal of the clamping circuit and the gate terminal of the transfer gate circuit. The gate terminal of the loading transistor circuit is supplied with a CEB (Chip Enable) signal. The gate terminal of the clamping circuit is connected with the drain terminal of the loading transistor circuit.

Abstract: Eight decoder circuits each of which comprising two transfer-gate-circuit transistors and two transistors for fixation of unselected level are connected in series and arranged in three hierarchies. Consequently, the decoder circuit is capable of selecting one output signal wire out of eight output signal wires by three address input signals so as to output an output of a high level to the selected output signal wire.