Abstract: A semiconductor device capable of charging that is less likely to cause deterioration of a power storage device is provided. The amount of a charging current is adjusted in accordance with the ambient temperature. Charging under low-temperature environments is performed with a reduced charging current. When the ambient temperature is too low or too high, the charging is stopped. Measurement of the ambient temperature is performed with a memory element using an oxide semiconductor. The use of a memory element using an oxide semiconductor enables measurement of the ambient temperature and retention of the temperature information to be performed at the same time.

Abstract: A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.

Abstract: According to an embodiment, an etching method includes forming a first layer on a substrate having a main surface including first and second regions adjacent to each other, the first layer including a portion covering the first region and having a plurality of openings or one or more openings defining a plurality of island-shaped portions, and the first layer further including a portion as a continuous layer covering the second region, forming a catalyst layer an a portion(s) of the main surface exposed in the openings by plating, forming a second layer to cover a portion of the catalyst layer adjacent to a boundary between the first and second regions and expose a portion of the catalyst layer spaced apart from the boundary, and etching the substrate in a presence of the catalyst layer and the second layer.

Abstract: In general, according to one embodiment, there is provided a method of manufacturing a structure. The method includes forming a recess in a semiconductor substrate; oxidizing at least a bottom inner surface of the recess; and providing at least the bottom inner surface of the recess with a liquid capable of dissolving an oxide of a semiconductor substrate material.

Abstract: According to one embodiment, an etching apparatus includes a first container including an opening covered by a semiconductor substrate; a second container including an opening covered by a catalyst layer; a first flow path configured to communicate with the first container; a second flow path configured to communicate with the second container; a cation exchange film interposed between the first flow path and the second flow path and allowing at least protons to pass through; and an electric field applier configured to apply an electric field to the semiconductor substrate.

Abstract: According to one embodiment, an etching method includes etching a surface made of a semiconductor and having a catalyst layer formed on the surface, by an etching agent in contact with the surface. The catalyst layer contains noble metal. The etching agent contains an oxidizer, a corrosive agent, and a N-containing polymer agent.

Abstract: According to an embodiment, a semiconductor device includes a layer stack including a conductive substrate containing semiconductor material and including a first main surface provided with one or more recesses and a second main surface opposite to the first main surface, a conductive layer covering at least part of the first main surface and side walls and bottom surfaces of the one or more recesses, and a dielectric layer interposed between the conductive substrate and the conductive layer, the conductive layer and a portion of the conductive substrate adjacent to the dielectric layer being an upper electrode and a lower electrode of a capacitor, respectively, an insulating layer provided on the capacitor or on the second main surface, and an inductor provided on the insulating layer at a position of the capacitor.

Abstract: According to an embodiment, an etching method includes forming a first layer on a substrate having a main surface including first and second regions adjacent to each other, the first layer including a portion covering the first region and having a plurality of openings or one or more openings defining a plurality of island-shaped portions, and the first layer further including a portion as a continuous layer covering the second region, forming a catalyst layer an a portion(s) of the main surface exposed in the openings by plating, forming a second layer to cover a portion of the catalyst layer adjacent to a boundary between the first and second regions and expose a portion of the catalyst layer spaced apart from the boundary, and etching the substrate in a presence of the catalyst layer and the second layer.

Abstract: According to an embodiment, an etching method includes forming an uneven structure including a protruding portion on a surface of a semiconductor substrate, the protruding portion having a reverse tapered cross-sectional shape; forming a catalyst layer on the surface of the semiconductor substrate at a top surface of the protruding portion, the catalyst layer including a noble metal; and supplying an etching solution to the catalyst layer to etch the semiconductor substrate with an assist from the noble metal as a catalyst.

Abstract: A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.

Abstract: A semiconductor device includes a redistribution layer, a bump bonded to a first surface of the redistribution layer, and a chip bonded to a second surface of the redistribution layer. The redistribution layer includes an insulating layer, a conductive member connecting the bump to the chip and being provided inside the insulating layer, a bonding electrode connected between the conductive member and the bump, and a conductive layer provided between the insulating layer and the conductive member and between the bonding electrode and the conductive member. A resistivity of the conductive member is lower than a resistivity of the conductive layer.

Abstract: A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.

Abstract: A method for manufacturing a semiconductor device includes forming first and second interconnect layers on first and second substrates, respectively; adhering the first and second substrates so that the back surfaces thereof face each other; bonding first and second semiconductor chips on the first and second interconnect layers, respectively; forming first and second molded bodies on the first and second substrates, respectively, while the first and second substrates are adhered; and detaching the first and second molded bodies from the first and second substrates. The first molded body includes the first interconnect layer, the first semiconductor chip and a first resin layer covering the first semiconductor chip on the first interconnect layer. The second molded body includes the second interconnect layer, the second semiconductor chip and a second resin layer covering the second semiconductor chip on the second interconnect layer. The first and second resin layers are formed simultaneously.

Abstract: According to one embodiment, a carrier includes a support substrate; a release layer provided on the support substrate; a first adhesion layer provided between the support substrate and the release layer; and a protective layer provided between the support substrate and the first adhesion layer. A thickness of the protective layer is thicker than a thickness of the release layer and a thickness of the first adhesion layer.

Abstract: According to one embodiment, a semiconductor device includes a re-interconnection layer, bumps, chips, and a resin member. The bumps are provided on a first surface of the re-interconnection layer. The chips are stacked on a second surface of the re-interconnection layer. The resin member is provided on the second surface, and covers the chips. The re-interconnection layer includes an insulating layer, an interconnection, a first via, an electrode layer, and a second via. The interconnection is provided in the insulating layer. The first via is provided in the insulating layer and connected to the interconnection. The electrode layer is provided in the insulating layer, formed of a metal material different from a material of the first via, exposed on the first surface, and connected to the first via and the bumps. The second via is provided in the insulating layer, and connected to the interconnection and the chips.

Abstract: A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.

Abstract: A semiconductor device includes a redistribution layer, a bump bonded to a first surface of the redistribution layer, and a chip bonded to a second surface of the redistribution layer. The redistribution layer includes an insulating layer, a conductive member connecting the bump to the chip and being provided inside the insulating layer, a bonding electrode connected between the conductive member and the bump, and a conductive layer provided between the insulating layer and the conductive member and between the bonding electrode and the conductive member. A resistivity of the conductive member is lower than a resistivity of the conductive layer.

Abstract: According to one embodiment, a semiconductor device includes a re-interconnection layer, bumps, chips, and a resin member. The bumps are provided on a first surface of the re-interconnection layer. The chips are stacked on a second surface of the re-interconnection layer. The resin member is provided on the second surface, and covers the chips. The re-interconnection layer includes an insulating layer, an interconnection, a first via, an electrode layer, and a second via. The interconnection is provided in the insulating layer. The first via is provided in the insulating layer and connected to the interconnection. The electrode layer is provided in the insulating layer, formed of a metal material different from a material of the first via, exposed on the first surface, and connected to the first via and the bumps. The second via is provided in the insulating layer, and connected to the interconnection and the chips.

Abstract: a method of fabricating a semiconductor device is described below. The method includes stacking a plurality of semiconductor chips on each of regions in a substrate having a plurality of first grooves extending in a first direction and a plurality of second grooves extending in a second direction intersecting the first direction, the region being defined by the first grooves and the second grooves, providing an encapsulation portion covering a side of the substrate on which the semiconductor chips are stacked, removing a surface portion of the substrate on the opposite side to the side on which the semiconductor chips are stacked to expose the first grooves and the second grooves, and cutting the encapsulation portion along the first grooves and of second grooves. The device and the method can provide higher productivity.

Abstract: a method of fabricating a semiconductor device is described below. The method includes stacking a plurality of semiconductor chips on each of regions in a substrate having a plurality of first grooves extending in a first direction and a plurality of second grooves extending in a second direction intersecting the first direction, the region being defined by the first grooves and the second grooves, providing an encapsulation portion covering a side of the substrate on which the semiconductor chips are stacked, removing a surface portion of the substrate on the opposite side to the side on which the semiconductor chips are stacked to expose the first grooves and the second grooves, and cutting the encapsulation portion along the first grooves and of second grooves. The device and the method can provide higher productivity.