Abstract: An imaging device having a function of processing an image is provided. The imaging device has an additional function such as image processing, can hold analog data obtained by an image capturing operation in a pixel, and can extract data obtained by multiplying the analog data by a predetermined weight coefficient. Difference data between adjacent light-receiving devices can be obtained in a pixel, and data on luminance gradient can be obtained. When the data is taken in a neural network or the like, inference of distance data or the like can be performed. Since enormous volume of image data in the state of analog data can be held in pixels, processing can be performed efficiently.

Abstract: A case, in which an inner bottom surface is formed, and a chuck tool in which a lower surface is formed are provided. The inner bottom surface is a concave surface. The lower surface is a concave surface. An elongated member chucking apparatus changes an orientation of an elongated member inside the case to a predetermined orientation with respect to the chuck tool by sandwiching the elongated member between the inner bottom surface and the lower surface. The elongated member is held by the chuck tool in the predetermined orientation.

Abstract: The present invention is provided with a case, in which an inner bottom surface is formed, and a chuck tool in which a lower surface is formed. The inner bottom surface is a concave surface. The lower surface is a concave surface. An elongated member chucking apparatus changes an orientation of an elongated member inside the case to a predetermined orientation with respect to the chuck tool by sandwiching the elongated member between the inner bottom surface and the lower surface. The elongated member is held by the chuck tool in the predetermined orientation.

Abstract: An external terminal receives an external signal so as to access the first and second memory chips. The test starting terminal receives a test starting signal activated when the first or second memory chip is tested and inactivated when the first and second memory chips are normally operated. The access signal generator converts the external signal to a memory access signal of the first memory chip. The first selector selects the external signal, which is a test signal, during activation of the test starting signal, selects the memory access signal during the inactivation of the test starting signal. That is, during the test modes, the first memory chip can be directly accessed from the exterior. For this reason, the test program for testing the first memory chip alone can be diverted as the test program following an assembly of the semiconductor device.

Abstract: A non-volatile includes a memory cell array for storing data, a decryption circuit for decrypting data read from the memory cell array using a prescribed computing process, and a decryption control circuit for activating the decryption circuit according to an inputted decryption command during a read operation.

Abstract: A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern(s) for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern(s) outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern(s) (the first test mode) generated within the logic chip or the external test pattern (the second test mode) supplied from the exterior.

Abstract: A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern in the first test mode, generated within the logic chip, or the external test pattern in the second test mode, supplied from the exterior.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array which includes nonvolatile memory cells, and a control circuit which responds to a first command by performing a first batch erasure with respect to a selected group of the memory cells, and responds to a second command by performing a second batch erasure with respect to the selected group of the memory cells, the first batch erasure including preprogramming, erasure, and over-erasure correction in this sequence, and the second batch erasure including over-erasure correction, preprogramming, erasure, and over-erasure correction in this sequence.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array which includes nonvolatile memory cells, and a control circuit which responds to a first command by performing a first batch erasure with respect to a selected group of the memory cells, and responds to a second command by performing a second batch erasure with respect to the selected group of the memory cells, the first batch erasure including preprogramming, erasure, and over-erasure correction in this sequence, and the second batch erasure including over-erasure correction, preprogramming, erasure, and over-erasure correction in this sequence.

Abstract: A non-volatile memory comprises: a memory cell array for storing data; a decryption circuit for decrypting data read from the memory cell array using a prescribed computing process; and a decryption control circuit for, in response to a decryption command supplied from outside, activating the decryption circuit during a read operation. During writing time in the abovementioned memory, a user who is authorized to write data to memory and then read the data writes encoded (for example, inverted) data to certain address, and writes data which are not encoded (not inverted) to an address other than that. If the user is authorized, then the user knows the encoded addresses and non-encoded addresses, and therefore the user can give a decryption command when reading data from the encoded addresses during reading time, thereby activating the decryption circuit stored in the device such that the decrypted data can be outputted.

Abstract: A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern(s) for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern(s) outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern(s) (the first test mode) generated within the logic chip or the external test pattern (the second test mode) supplied from the exterior.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array, a control circuit which repeatedly perform an automatic erasure operation with respect to an entirety of the memory cell array, the automatic erasure operation including a preparatory write operation prior to an erasure operation and a following erasure operation, and a counter which counts how many times the automatic erasure operation is performed with respect to the entirety of the memory cell array, wherein the control circuit stops the automatic erasure operation in response to an event that the counter counts a desired number.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array, a control circuit which repeatedly perform an automatic erasure operation with respect to an entirety of the memory cell array, the automatic erasure operation including a preparatory write operation prior to an erasure operation and a following erasure operation, and a counter which counts how many times the automatic erasure operation is performed with respect to the entirety of the memory cell array, wherein the control circuit stops the automatic erasure operation in response to an event that the counter counts a desired number.