Patents by Inventor Takeaki Sato

Takeaki Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9009387
    Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
  • Patent number: 8756401
    Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
  • Patent number: 8347024
    Abstract: A memory system includes a non-volatile semiconductor memory that includes a plurality of blocks, each of the blocks being a data erasing unit; an erasing time monitoring unit that monitors time required for erasing data from the non-volatile semiconductor memory; a management table for managing the erasing time on a unit of each of the blocks; and a wear-leveling control unit that levels number of rewriting across the blocks based on the management table. The memory system accommodates variations among lots, individual pieces, and blocks, thereby performing highly-accurate wear leveling.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: January 1, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeaki Sato
  • Patent number: 8230156
    Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
  • Patent number: 8169829
    Abstract: A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a predetermined record state great based on a count of a counter in a record operation, the memory system sets a flag added to the data sequence to indicate that the reverse processing has been performed, and performs re-reverse processing on the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: May 1, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeaki Sato
  • Publication number: 20110191552
    Abstract: A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a predetermined record state great based on a count of a counter in a record operation, the memory system sets a flag added to the data sequence to indicate that the reverse processing has been performed, and performs re-reverse processing on the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation.
    Type: Application
    Filed: April 8, 2011
    Publication date: August 4, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Takeaki SATO
  • Patent number: 7936609
    Abstract: A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a predetermined record state great based on a count of a counter in a record operation, the memory system sets a flag added to the data sequence to indicate that the reverse processing has been performed, and performs re-reverse processing on the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: May 3, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeaki Sato
  • Publication number: 20110078402
    Abstract: A memory system includes a non-volatile semiconductor memory that includes a plurality of blocks, each of the blocks being a data erasing unit; an erasing time monitoring unit that monitors time required for erasing data from the non-volatile semiconductor memory; a management table for managing the erasing time on a unit of each of the blocks; and a wear-leveling control unit that levels number of rewriting across the blocks based on the management table. The memory system accommodates variations among lots, individual pieces, and blocks, thereby performing highly-accurate wear leveling.
    Type: Application
    Filed: April 1, 2010
    Publication date: March 31, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Takeaki SATO
  • Publication number: 20100138606
    Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
    Type: Application
    Filed: February 8, 2010
    Publication date: June 3, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiyuki TANAKA, Makoto YATABE, Takeaki SATO, Kazuya KAWAMOTO
  • Publication number: 20100020619
    Abstract: A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a predetermined record state great based on a count of a counter in a record operation, the memory system sets a flag added to the data sequence to indicate that the reverse processing has been performed, and performs re-reverse processing on the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation.
    Type: Application
    Filed: February 23, 2009
    Publication date: January 28, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Takeaki SATO
  • Publication number: 20100023680
    Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
    Type: Application
    Filed: September 22, 2009
    Publication date: January 28, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiyuki TANAKA, Makoto YATABE, Takeaki SATO, Kazuya KAWAMOTO
  • Patent number: 7394704
    Abstract: A non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: July 1, 2008
    Assignees: Kabushiki Kaisha Toshiba, Sandisk Corporation
    Inventors: Tomoharu Tanaka, Khandker N. Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato
  • Publication number: 20080059695
    Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 6, 2008
    Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
  • Patent number: 7054991
    Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
  • Publication number: 20060077712
    Abstract: Disclosed is a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.
    Type: Application
    Filed: November 30, 2005
    Publication date: April 13, 2006
    Inventors: Tomoharu Tanaka, Khandker Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato
  • Patent number: 6990018
    Abstract: A non-volatile semiconductor memory device including a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: January 24, 2006
    Assignees: Kabushiki Kaisha Toshiba, SanDisk Corporation
    Inventors: Tomoharu Tanaka, Khandker N. Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato
  • Patent number: 6845438
    Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: January 18, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
  • Publication number: 20050007865
    Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
    Type: Application
    Filed: August 6, 2004
    Publication date: January 13, 2005
    Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
  • Publication number: 20050005059
    Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
    Type: Application
    Filed: February 25, 2004
    Publication date: January 6, 2005
    Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
  • Publication number: 20040257874
    Abstract: Disclosed is a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.
    Type: Application
    Filed: April 14, 2004
    Publication date: December 23, 2004
    Inventors: Tomoharu Tanaka, Khandker N. Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato