Patents by Inventor Takeaki Sato
Takeaki Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9009387Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.Type: GrantFiled: February 8, 2010Date of Patent: April 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
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Patent number: 8756401Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.Type: GrantFiled: August 6, 2004Date of Patent: June 17, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
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Patent number: 8347024Abstract: A memory system includes a non-volatile semiconductor memory that includes a plurality of blocks, each of the blocks being a data erasing unit; an erasing time monitoring unit that monitors time required for erasing data from the non-volatile semiconductor memory; a management table for managing the erasing time on a unit of each of the blocks; and a wear-leveling control unit that levels number of rewriting across the blocks based on the management table. The memory system accommodates variations among lots, individual pieces, and blocks, thereby performing highly-accurate wear leveling.Type: GrantFiled: April 1, 2010Date of Patent: January 1, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Takeaki Sato
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Patent number: 8230156Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.Type: GrantFiled: October 31, 2007Date of Patent: July 24, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
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Patent number: 8169829Abstract: A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a predetermined record state great based on a count of a counter in a record operation, the memory system sets a flag added to the data sequence to indicate that the reverse processing has been performed, and performs re-reverse processing on the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation.Type: GrantFiled: April 8, 2011Date of Patent: May 1, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Takeaki Sato
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Publication number: 20110191552Abstract: A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a predetermined record state great based on a count of a counter in a record operation, the memory system sets a flag added to the data sequence to indicate that the reverse processing has been performed, and performs re-reverse processing on the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation.Type: ApplicationFiled: April 8, 2011Publication date: August 4, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Takeaki SATO
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Patent number: 7936609Abstract: A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a predetermined record state great based on a count of a counter in a record operation, the memory system sets a flag added to the data sequence to indicate that the reverse processing has been performed, and performs re-reverse processing on the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation.Type: GrantFiled: February 23, 2009Date of Patent: May 3, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Takeaki Sato
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Publication number: 20110078402Abstract: A memory system includes a non-volatile semiconductor memory that includes a plurality of blocks, each of the blocks being a data erasing unit; an erasing time monitoring unit that monitors time required for erasing data from the non-volatile semiconductor memory; a management table for managing the erasing time on a unit of each of the blocks; and a wear-leveling control unit that levels number of rewriting across the blocks based on the management table. The memory system accommodates variations among lots, individual pieces, and blocks, thereby performing highly-accurate wear leveling.Type: ApplicationFiled: April 1, 2010Publication date: March 31, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Takeaki SATO
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Publication number: 20100138606Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.Type: ApplicationFiled: February 8, 2010Publication date: June 3, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiyuki TANAKA, Makoto YATABE, Takeaki SATO, Kazuya KAWAMOTO
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Publication number: 20100020619Abstract: A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a predetermined record state great based on a count of a counter in a record operation, the memory system sets a flag added to the data sequence to indicate that the reverse processing has been performed, and performs re-reverse processing on the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation.Type: ApplicationFiled: February 23, 2009Publication date: January 28, 2010Applicant: Kabushiki Kaisha ToshibaInventor: Takeaki SATO
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Publication number: 20100023680Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.Type: ApplicationFiled: September 22, 2009Publication date: January 28, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiyuki TANAKA, Makoto YATABE, Takeaki SATO, Kazuya KAWAMOTO
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Patent number: 7394704Abstract: A non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.Type: GrantFiled: November 30, 2005Date of Patent: July 1, 2008Assignees: Kabushiki Kaisha Toshiba, Sandisk CorporationInventors: Tomoharu Tanaka, Khandker N. Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato
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Publication number: 20080059695Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.Type: ApplicationFiled: October 31, 2007Publication date: March 6, 2008Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
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Patent number: 7054991Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.Type: GrantFiled: February 25, 2004Date of Patent: May 30, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
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Publication number: 20060077712Abstract: Disclosed is a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.Type: ApplicationFiled: November 30, 2005Publication date: April 13, 2006Inventors: Tomoharu Tanaka, Khandker Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato
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Patent number: 6990018Abstract: A non-volatile semiconductor memory device including a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.Type: GrantFiled: April 14, 2004Date of Patent: January 24, 2006Assignees: Kabushiki Kaisha Toshiba, SanDisk CorporationInventors: Tomoharu Tanaka, Khandker N. Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato
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Patent number: 6845438Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.Type: GrantFiled: August 7, 1998Date of Patent: January 18, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
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Publication number: 20050007865Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.Type: ApplicationFiled: August 6, 2004Publication date: January 13, 2005Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
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Publication number: 20050005059Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.Type: ApplicationFiled: February 25, 2004Publication date: January 6, 2005Inventors: Yoshiyuki Tanaka, Makoto Yatabe, Takeaki Sato, Kazuya Kawamoto
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Publication number: 20040257874Abstract: Disclosed is a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.Type: ApplicationFiled: April 14, 2004Publication date: December 23, 2004Inventors: Tomoharu Tanaka, Khandker N. Quader, Hiroyuki Dohmae, Atsushi Inoue, Takeaki Sato