Abstract: A display driver comprises an interface and signal supply circuitry. The interface is configured to receive image data. The signal supply circuitry is configured to supply at least one drive control signal to a display panel based on a detection of a data error in the image data associated with a first horizontal line in a first vertical sync period, causing a first pixel circuit and a second pixel circuit hold, in the first vertical sync period, first hold voltages based in part on at least one drive control signal and second hold voltages held in a second vertical sync period prior to the first vertical sync period. The first pixel circuit is associated with the first horizontal line, and the second pixel circuit is associated with a second horizontal line and driven after the first pixel circuit.

Abstract: An integrated circuit includes a plurality of signal inputs, a receiver, calibration circuitry, and input switch circuitry. The receiver includes differential input terminals. The calibration circuitry is configured to calibrate an input offset between the differential input terminals of the receiver in response to the integrated circuit being placed in a calibration mode. The input switch circuitry is configured to switch electrical connections between the plurality of signal inputs and the differential input terminals of the receiver in response to the integrated circuit being placed in a mode different from the calibration mode. The input switch circuitry is further configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver in response to the integrated circuit being placed in the calibration mode.

Abstract: An integrated circuit includes a plurality of signal inputs, a receiver, calibration circuitry, and input switch circuitry. The receiver includes differential input terminals. The calibration circuitry is configured to calibrate an input offset between the differential input terminals of the receiver in response to the integrated circuit being placed in a calibration mode. The input switch circuitry is configured to switch electrical connections between the plurality of signal inputs and the differential input terminals of the receiver in response to the integrated circuit being placed in a mode different from the calibration mode. The input switch circuitry is further configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver in response to the integrated circuit being placed in the calibration mode.

Abstract: An integrated circuit device comprises: a resin film that is flexible; a plurality of traces bonded on a surface of the resin film and arrayed in a specific direction; an IC chip bonded on the surface of the resin film, located offset to the traces in a direction perpendicular to the specific direction, and connected to the traces; and a protection pattern formed on the surface of the resin film, located in the specific direction with respect to a disposition region in which the IC chip and/or the traces are disposed, and formed of the same material as that of the traces.

Abstract: A receiver device comprises one or more differential receivers configured to respectively output single ended signals, one or more delay compensation circuitries configured to delay the single ended signals, clock recovery circuitry configured to generate a recovered clock signal based on a compensated single ended signals respectively outputted from the delay compensation circuitries, and one or more latch circuitries configured to respectively latch the compensated single ended signals in synchronization with the recovered clock signal.

Abstract: A display driver comprises an interface and signal supply circuitry. The interface is configured to receive image data. The signal supply circuitry is configured to supply at least one drive control signal to a display panel based on a detection of a data error in the image data associated with a first horizontal line in a first vertical sync period, causing a first pixel circuit and a second pixel circuit hold, in the first vertical sync period, first hold voltages based in part on at least one drive control signal and second hold voltages held in a second vertical sync period prior to the first vertical sync period. The first pixel circuit is associated with the first horizontal line, and the second pixel circuit is associated with a second horizontal line and driven after the first pixel circuit.

Abstract: Semiconductor circuitry comprises a plurality of signal transition detectors and dynamic OR circuitry. The plurality of signal transition detectors are configured to respectively output detection signals, each of the detection signals being based on a transition of at least one of a plurality of signals. The dynamic OR circuitry is configured to output a recovered clock signal based on a logical sum of the detection signals.

Abstract: Semiconductor circuitry comprises a plurality of signal transition detectors and dynamic OR circuitry. The plurality of signal transition detectors are configured to respectively output detection signals, each of the detection signals being based on a transition of at least one of a plurality of signals. The dynamic OR circuitry is configured to output a recovered clock signal based on a logical sum of the detection signals.

Abstract: A receiver device comprises one or more differential receivers configured to respectively output single ended signals, one or more delay compensation circuitries configured to delay the single ended signals, clock recovery circuitry configured to generate a recovered clock signal based on a compensated single ended signals respectively outputted from the delay compensation circuitries, and one or more latch circuitries configured to respectively latch the compensated single ended signals in synchronization with the recovered clock signal.

Abstract: A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

Abstract: A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.

Abstract: A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

Abstract: A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.