Abstract: A semiconductor device comprising a drain and source region formed in a semiconductor substrate is provided. In order to provide a semiconductor device having a high packing density of the circuit elements, the contact windows for the source region and substrate region are combined into one opening in the source region. A common contact region is formed in a portion of the contact window for the source region by doping opposite conductivity type impurities. The depth of the converted region is deep enough to extend to the substrate. By connecting the source region and the substrate region in the common contact hole, the positioning margin and the wiring for connecting them are unnecessary and thus, the packing density of the devices in the MIS IC is increased.

Abstract: In order to provide semiconductor devices having a high switching speed and high packing density of the circuit elements, a p-MOSFET of a CMOS IC is formed on an n-type well which has a higher impurity concentration compared with that of the n-type substrate region and which is formed at selected portions under the p-MOSFET. In order to decrease the capacitance of the source and drain of the p-MOSFET, the n-type well regions are selectively formed only at portions under the gate electrode and the field insulating layer, and a junction of the p.sup.+ -type drain and source region is formed directly on a part of the n.sup.- -type substrate region. As a result, the latch-up phenomenon can be suppressed and the junction capacitance of the devices becomes smaller. Therefore, the switching speed and the packing density of the CMOS IC are improved.

Abstract: A basic cell of a gate array device comprises a substrate, a plurality of source/drain diffusion regions being formed in the substrate, at least one gate electrode being located between the adjacent source/drain diffusion regions, a substrate contact region being formed in the substrate and being located in the vicinity of the source/drain diffusion regions, and an insulation film being provided on the source/drain regions and the gate electrode and being provided with contact hole forming regions at which contact holes are to be formed so as to form a plurality of interconnecting channels for making an electric connection between desired regions. Each of the source/drain diffusion regions adjacent to the substrate contact region has a narrower portion located under one interconnecting channel specifically for making one substrate contact and a wider portion located under the other interconnecting channels.

Abstract: A semiconductor device comprises an insulating substrate; an island shaped single-crystalline semiconductor layer on the insulating substrate; and a conductor pattern provided on the single-crystalline semiconductor layer through the insulating layer and extending onto the insulating substrate. The edge region of the single-crystalline semiconductor layer, which region is below the conductor pattern, in the insulating layer is selectively formed with a larger thickness than other portions of the insulating layer.

Abstract: A metal insulator semiconductor device having a high breakdown voltage characteristic and a fabricating method thereof. The device comprises a depletion region and an enhancement region formed in a semiconductor substrate under a gate electrode. The depletion region is formed adjacent to an offset region formed around a drain region. The enhancement type channel region is formed between the depletion region and a source region is as to have an extremely short channel length. The enhancement type channel region has a first type impurity concentration that is higher than that of the semiconductor substrate. The depletion region has a second type of impurity concentration that is opposite to the first type and lower than that of the offset region in order to increase the breakdown voltage at the drain region. The short channel length is formed by applying a diffusion self-aligning method.

Abstract: A semiconductor device comprises a semiconductor chip having main power supply lines which are arranged in peripheral regions in the vicinity of edges of the semiconductor chip and which are formed with multi-level metallization. The main power supply lines are formed with arrangements in that layers of the same potential face each other through an insulating layer in chip corner regions adjacent to corners of the semiconductor chip.

Abstract: A complementary type semiconductor device comprises n-channel FETs and three types of p-channel FETs formed in an n.sup.- -type semiconductor substrate. First p-channel FETs and n-channel FETs, both having deep well regions are used for input/output circuits disposed in peripheral areas of the substrate such that these transistors are connected directly to external circuits through bonding wires and the like. The transistors are seldom disturbed by undesirable noises from the external circuits, and the FETs are thus suitable for preventing the latchup effect of the circuits. The other second p-channel FETS have n-type sub-well regions beneath their gate insulator layers, and thus, have relatively small junction capacitances. These FETs are used in circuits needed for high switching speed and are disposed in the inner area of the substrate.

Abstract: A semiconductor device having an SOI structure comprises an insular single crystal silicon body formed on an insulator layer, a first region of a first type semiconductor and source and drain regions of a second type semiconductor provided in the insular single crystal silicon body so that the first region is provided between the source and drain regions, a second region of the first type semiconductor in contact with the first region formed along a side of the source and drain regions, and a contact region of the first type semiconductor having an impurity density higher than those of the first and second regions formed in contact with the second region, so that a fixed voltage can be applied to the first region via the contact region.

Abstract: A method of fabricating a narrow channel width IG-FET which includes compensating for impurities diffused into the channel region from the channel stopper, thereby providing the IG-FET with a threshold providing the IG-FET with a threshold voltage establishing at a level substantially the same as that of conventional wider channel width IG-FETs. According to the present invention, impurities having a conductivity type opposite to that of the impurities diffused from the channel stopper are selectively implanted in at least the channel region of the narrow channel width IG-FET, to compensate the diffused impurities. Impurities for channel doping are then implanted to adjust the threshold voltage.

Abstract: A protection circuit for inner elements such as metal insulator semiconductor (MIS) field effect transistors in a semiconductor device of high packing density has been improved. The protection circuit comprises protective elements of two types. One type has a deep diffusion region providing the element with high surge capacity, that is an ability to withstand the energy of an incoming surge, and the other type has a shallow diffusion region providing a low breakdown voltage. With a combination of these two types of protective element, the protection circuit can withstand high energy of an input surge and, at the same time, provide a low protection voltage suitable to protect the inner elements from breakdown.

Abstract: An I/O protection device which protects the IC from noise especially from static charge break down is disclosed. A resistance body made from polysilicon is provided between the I/O pad and I/O circuit of the IC. The resistance body may be formed over the gate oxide or field oxide layer. Beneath the resistance body is formed a diffusion region having an opposite conductivity type to that of the substrate. The diffusion region is connected electrically in parallel to the resistance body. In some cases, the diffusion region may be connected at only one point.

Abstract: A semiconductor integrated device and a method for manufacturing the same, the device comprising an internal semiconductor integrated circuit which includes N-MOS transistors, and a P-MOS output transistor having a source connected to a voltage power supply. The drain of the P-MOS transistor is connected to an output terminal and the output terminal is operatively connected to a device driven by the P-MOS transistor.

Abstract: A protection element responsible for protecting a semiconductor element included in a semiconductor device from a voltage higher than the voltage which the semiconductor element is allowed to receive, the protection element virtually being a lateral bipolar transistor, in which an improvement is made to increase the voltage at which the protection element operates. The improvement being realized by separating the emitter from a region containing an impurity at a high concentration and which is a portion of the base of the lateral bipolar transistor.

Abstract: A read only memory has a plurality of memory cells each of which comprises a transistor.The transistor in each memory cell is either an offset gate transistor or an enhancement transistor.A pair of transistors in adjacent memory cells are connected to a bit line via a common connection means.

Abstract: A method for producing a semiconductor device which includes forming, in a well having the first conductivity type and selectively provided in a semiconductor substrate having a second conductivity type opposite the first conductivity type, two first impurity diffusion regions having the second conductivity type. In an exposed surface region of the substrate, the two second impurity diffusion regions, respectively, forming, in the well and the exposed surface region of the substrate, a third impurity diffusion region by implanting impurity ions having a P-type or N-type into the semiconductor substrate. The method also includes forming an electric current channel either between the two first impurity diffusion regions or between the two second impurity diffusion regions, thereby forming various integrated circuits by changing the wiring channel.

Abstract: A plurality of MIS-type transistors are arranged in a matrix, with each one of these MIS-type transistors corresponding to one memory information bit. These MIS-type transistors are formed so as to store and read binary information in accordance with whether the characteristic of these MIS-type transistors is normally on or normally off. At least one of the source and drain regions of the MIS-type transistors having a normally on characteristic is formed with a higher impurity density or at a greater depth compared with the regions of the MIS-type transistors having a normally off characteristic.

Abstract: In a process for producing a semiconductor device, particularly an MIS structure semiconductor device, an electrode, which is in ohmic contact with the semiconductor substrate, is usually formed on the surface which is opposite to the surface having MIS FETs. However, in a recently developed process, the electrode mentioned above is formed on the semiconductor substrate surface on which the MIS FETs are formed, and the electrode is in ohmic contact with the substrate through a short-circuit of a PN junction formed on such semiconductor substrate surface. However, a so formed electrode is liable to break. In the present invention, wherein a masking layer covers the substrate-contact region during the production of the MIS FETs, the electrode mentioned above is in an ohmic contact with the electrode not through the PN junction and the problem of breaking occurs seldom.