Abstract: A data processing apparatus includes a zoom circuit for displaying and a zoom circuit for recording. The zoom circuit for displaying performs a zoom process using a least square method or linear interpolation on image data from a YUV conversion circuit so as to create display image data. On an LCD monitor, an image based on the display image data thus created is displayed. Furthermore, the zoom circuit for recording performs a zoom process using spline interpolation or linear interpolation on image data from the YUV conversion circuit so as to create recording image data. The zoom process for recording is executed in parallel with the zoom process for displaying. The recording image data thus created is recorded in a recording medium.

Abstract: A digital camera includes a signal processing circuit. The signal processing circuit makes signal processing on the camera data read from a camera data area of an SDRAM to produce YUV data for record. A thin-out circuit makes a thin-out processing on the recording YUV data to produce YUV data for display. The display YUV data and the recording YUV data thus produced are written respectively to a display data area and a recording data area of the SDRAM and thereafter processed for display on a display and record to a flash memory. The access speed to SDRAM is 48 MHz and the processing speed of the signal processing circuit and thin-out circuit is 12 MHz. Consequently, the YUV data for display and YUV data for record is written concurrently with reading out of the camera data.

Abstract: A data processing apparatus includes a zoom circuit for displaying and a zoom circuit for recording. The zoom circuit for displaying performs a zoom process using a least square method or linear interpolation on image data from a YUV conversion circuit so as to create display image data. On an LCD monitor, an image based on the display image data thus created is displayed. Furthermore, the zoom circuit for recording performs a zoom process using spline interpolation or linear interpolation on image data from the YUV conversion circuit so as to create recording image data. The zoom process for recording is executed in parallel with the zoom process for displaying. The recording image data thus created is recorded in a recording medium.

Abstract: A digital camera includes a signal processing circuit. The signal processing circuit makes signal processing on the camera data read from a camera data area of an SDRAM to produce YUV data for record. A thin-out circuit makes a thin-out processing on the recording YUV data to produce YUV data for display. The display YUV data and the recording YUV data thus produced are written respectively to a display data area and a recording data area of the SDRAM and thereafter processed for display on a display and record to a flash memory. The access speed to SDRAM is 48 MHz and the processing speed of the signal processing circuit and thin-out circuit is 12 MHz. Consequently, the YUV data for display and YUV data for record is written concurrently with reading out of the camera data.

Abstract: A digital camera includes a signal processing circuit. The signal processing circuit makes signal processing on the camera data read from a camera data area of an SDRAM to produce YUV data for record. A thin-out circuit makes a thin-out processing on the recording YUV data to produce YUV data for display. The display YUV data and the recording YUV data thus produced are written respectively to a display data area and a recording data area of the SDRAM and thereafter processed for display on a display and record to a flash memory. The access speed to SDRAM is 48 MHz and the processing speed of the signal processing circuit and thin-out circuit is 12 MHz. Consequently, the YUV data for display and YUV data for record is written concurrently with reading out of the camera data.

Abstract: A CCD is driven by a drive circuit, whereby an independent readout drive of all pixels is carried out. Data of 4 lines are input in parallel to a two-dimensional register array by 4 scanning line delay devices. Interpolation is carried out for every color signal of green, magenta, cyan and yellow by an interpolation processing circuit according to data corresponding to pixels of 4 rows and 6 columns. A color difference signal generation circuit carries out a color separation process on the basis of the color signal subjected to an interpolation process.

Abstract: A digital camera includes a signal processing circuit. The signal processing circuit makes signal processing on the camera data read from a camera data area of an SDRAM to produce YUV data for record. A thin-out circuit makes a thin-out processing on the recording YUV data to produce YUV data for display. The display YUV data and the recording YUV data thus produced are written respectively to a display data area and a recording data area of the SDRAM and thereafter processed for display on a display and record to a flash memory. The access speed to SDRAM is 48 MHz and the processing speed of the signal processing circuit and thin-out circuit is 12 MHz. Consequently, the YUV data for display and YUV data for record is written concurrently with reading out of the camera data.