Patents by Inventor Takehiko Sakamoto
Takehiko Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230212280Abstract: A method of treating systemic sclerosis in a patient administers an IL-23 specific antibody, e.g., guselkumab, at an initial dose and subsequent doses in order for the patient to respond to the antibody and meet one or more of the clinical endpoints.Type: ApplicationFiled: December 16, 2022Publication date: July 6, 2023Inventors: Takemichi Fukasawa, Sheng Gao, Nobukazu Kakui, Naoko Kawashima, Takayuki Kimura, Hitomi Morishima, Ernesto Munoz, Shawn Rose, Takehiko Sakamoto, Shinichi Sato, John Toso, Yoshifumi Ukyo, Ayumi Yoshizaki, Richuan Zheng
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Patent number: 10396029Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: GrantFiled: June 11, 2018Date of Patent: August 27, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koujirou Matsui, Takehiko Sakamoto, Kazuyuki Umezu, Tomoaki Uno
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Publication number: 20180294220Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: ApplicationFiled: June 11, 2018Publication date: October 11, 2018Inventors: Koujirou MATSUI, Takehiko SAKAMOTO, Kazuyuki UMEZU, Tomoaki UNO
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Patent number: 10068849Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: GrantFiled: March 17, 2016Date of Patent: September 4, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koujirou Matsui, Takehiko Sakamoto, Kazuyuki Umezu, Tomoaki Uno
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Publication number: 20160204252Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: ApplicationFiled: March 17, 2016Publication date: July 14, 2016Inventors: Koujirou MATSUI, Takehiko SAKAMOTO, Kazuyuki UMEZU, Tomoaki UNO
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Patent number: 9318434Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: GrantFiled: August 27, 2014Date of Patent: April 19, 2016Assignee: RENSAS ELECTRONICS CORPORATIONInventors: Koujirou Matsui, Takehiko Sakamoto, Kazuyuki Umezu, Tomoaki Uno
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Publication number: 20150137260Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.Type: ApplicationFiled: August 27, 2014Publication date: May 21, 2015Inventors: Koujirou MATSUI, Takehiko SAKAMOTO, Kazuyuki UMEZU, Tomoaki UNO
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Patent number: 8933264Abstract: To provide a method for producing an organic compound having a sulfo group by efficiently hydrolyzing an organic compound having a fluorosulfonyl group with a small number of steps with a small quantity of waste liquid. A method for producing an organic compound having a sulfo group, which comprises bringing an organic compound having a fluorosulfonyl group into contact with subcritical water at from 200 to 320° C. to convert the fluorosulfonyl group into a sulfo group.Type: GrantFiled: February 26, 2014Date of Patent: January 13, 2015Assignee: Asahi Glass Company, LimitedInventors: Atsushi Watakabe, Yoshitomi Morizawa, Hisao Hori, Takehiko Sakamoto, Tomoyuki Fujita, Kana Ishikawa
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Publication number: 20140179948Abstract: To provide a method for producing an organic compound having a sulfo group by efficiently hydrolyzing an organic compound having a fluorosulfonyl group with a small number of steps with a small quantity of waste liquid. A method for producing an organic compound having a sulfo group, which comprises bringing an organic compound having a fluorosulfonyl group into contact with subcritical water at from 200 to 320° C. to convert the fluorosulfonyl group into a sulfo group.Type: ApplicationFiled: February 26, 2014Publication date: June 26, 2014Applicant: ASAHI GLASS COMPANY, LIMITEDInventors: Atsushi WATAKABE, Yoshitomi MORIZAWA, Hisao HORI, Takehiko SAKAMOTO, Tomoyuki FUJITA, Kana ISHIKAWA
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Publication number: 20120013019Abstract: A signal line is formed in the a-th layer (a?2) of a multi-layered interconnect layer and a redistribution layer. A plain line is formed in the b-th layer (b<a) of the multi-layered interconnect layer and the redistribution layer and overlaps with the signal line when seen in a plan view. Two coplanar lines that are formed in the c-th layer (b?c?a) of the multi-layered interconnect layer and the redistribution layer, extend in parallel to the signal line when seen in a plan view, and interpose the signal line therebetween. A distance h from the signal line to the plain line is smaller than a distance w from the signal line to the coplanar lines. A power supply line, a ground line, and another signal line are not located within the range of the height equal to the distance w from the signal line above the signal line.Type: ApplicationFiled: July 12, 2011Publication date: January 19, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takehiko SAKAMOTO, Yasutaka NAKASHIBA
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Patent number: 7310040Abstract: The present invention provides an improved manufacturing stability of a semiconductor device provided with a spiral inductor. The semiconductor device 100 includes a silicon substrate 101, an element isolating oxide film embedded within the silicon substrate 101, a first insulating interlayer provided on the silicon substrate 101, a spiral inductor 120 provided on the first insulating interlayer, and a shielding layer, which is provided between the spiral inductor 120 and the silicon substrate 101, and elongates toward a direction along the surface of the substrate to provide a shield between the spiral inductor 120 and the silicon substrate 101. Then, a plurality of substrate remaining regions 131 formed by the silicon substrate 101 partially remaining in the element isolating oxide film in a form of islands from the upper viewpoint are selectively provided right under the polysilicon 105 in the region for forming the spiral inductor 120.Type: GrantFiled: November 7, 2005Date of Patent: December 18, 2007Assignee: NEC Electronics CorporationInventor: Takehiko Sakamoto
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Publication number: 20060097836Abstract: The present invention provides an improved manufacturing stability of a semiconductor device provided with a spiral inductor. The semiconductor device 100 includes a silicon substrate 101, an element isolating oxide film embedded within the silicon substrate 101, a first insulating interlayer provided on the silicon substrate 101, a spiral inductor 120 provided on the first insulating interlayer, and a shielding layer, which is provided between the spiral inductor 120 and the silicon substrate 101, and elongates toward a direction along the surface of the substrate to provide a shield between the spiral inductor 120 and the silicon substrate 101. Then, a plurality of substrate remaining regions 131 formed by the silicon substrate 101 partially remaining in the element isolating oxide film in a form of islands from the upper viewpoint are selectively provided right under the polysilicon 105 in the region for forming the spiral inductor 120.Type: ApplicationFiled: November 7, 2005Publication date: May 11, 2006Applicant: NEC ELECTRONIC CORPORATIONInventor: Takehiko Sakamoto
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Publication number: 20050258508Abstract: A semiconductor device includes a semiconductor substrate, and a multi-layered wiring arrangement formed on the semiconductor substrate and having insulating interlayers stacked in order thereon. A first inductor is formed on one of the insulating layers of the multi-layered wiring arrangement. A second inductor has a smaller size than the first inductor, and is formed on the same insulating interlayer as the first inductor, so that the second inductor is arranged inside of the first inductor.Type: ApplicationFiled: April 22, 2005Publication date: November 24, 2005Inventor: Takehiko Sakamoto