Abstract: In a microcomputer, a testing-purpose interrupt request signal generator generates a testing-purpose interrupt request signal, an interrupt request selecting register stores an interrupt request selection signal for making an interrupt request during testing effective, and at least one delay circuit generates one or more delayed interrupt request selection signals obtained by delaying the interrupt request selection signal by one or more delay times. Each of selection circuits selects either one of the interrupt request signals or the testing-purpose interrupt request signal based on the delayed interrupt request selection signal. The testing-purpose interrupt request signals output from the respective selection circuits at a different timing, can be sequentially input to the interrupt controller.

Abstract: There is provided a scan test system comprising: a semiconductor device including a scan register connected between an input/output pin on an analog input side and an internal system logic; a semiconductor device including a scan register connected between an input/output pin on an analog output side and an analog sensor; and an analog wiring connecting the input/output pins each other. Thus, the scan register can be chained to thereby constitute a boundary scan register chain, and thereby JTAG control can be carried out by use of TAPC. Therefore, monitoring inspection where probes are set up by high-density-assembling of semiconductor devices and the multiple pins of low-cost devices, can be achieved.

Abstract: A semiconductor chip is provided, with which presence of dead pins can be easily noticed and a process for controlling the potential at dead pins can be performed easily. An input/output controller (IOC) for coordinating the input/output of signals through individual pins (PN1 to PN8) includes an input/output buffer (BFa) and the input/output buffer (BFa) includes a switch (SW4a) and a switch (SW4b). A setting memory (STMa) for storing settings for control of the input/output of signals in the input/output buffer (BFa) contains a memory table and the memory table contains an item about the dead pin potential control process so that a power-supply potential (Vdd) or a ground potential (GND) can be applied to the dead pins, i.e. the fourth pin (PN4) and the fifth pin (PN4).

Abstract: In a memory access device, a memory address space of a Random Access Memory (RAM) is divided into blocks BK0 to BKn having continuous address areas. Address buses and data buses of a Central Processing Unit (CPU) and a Real Time Debugger (RTD) are connected to each of the blocks BK0 to BKn. The memory access control circuit checks whether memory blocks accessed by the CPU and the RTD are the same. The memory access control circuit permits simultaneous access by the CPU and the RTD to the memory blocks when the memory block accessed by the CPU and the RTD are not same.

Abstract: In a microcomputer, a testing-purpose interrupt request signal generator generates a testing-purpose interrupt request signal, an interrupt request selecting register stores an interrupt request selection signal for making an interrupt request during testing effective, and at least one delay circuit generates one or more delayed interrupt request selection signals obtained by delaying the interrupt request selection signal by one or more delay times. Each of selection circuits selects either one of the interrupt request signals or the testing-purpose interrupt request signal based on the delayed interrupt request selection signal. The testing-purpose interrupt request signals output from the respective selection circuits at a different timing, can be sequentially input to the interrupt controller.

Abstract: There is provided a boundary-scan test device incorporated into a semiconductor integrated circuit for running self-diagnostics on the semiconductor integrated circuit. The device comprises a bypass unit for, when a package in which the semiconductor integrated circuit is assembled does not have one or more corresponding external input/output pins associated with one or more predetermined boundary-scan registers, changing the length of a boundary-scan register chain that consists of a plurality of boundary-scan registers by bypassing the one or more predetermined boundary-scan registers according to a bypass control signal applied thereto.

Abstract: A semiconductor chip is provided, with which presence of dead pins can be easily noticed and a process for controlling the potential at dead pins can be performed easily. An input/output controller (IOC) for coordinating the input/output of signals through individual pins (PN1 to PN8) includes an input/output buffer (BFa) and the input/output buffer (BFa) includes a switch (SW4a) and a switch (SW4b). A setting memory (STMa) for storing settings for control of the input/output of signals in the input/output buffer (BFa) contains a memory table and the memory table contains an item about the dead pin potential control process so that a power-supply potential (Vdd) or a ground potential (GND) can be applied to the dead pins, i.e. the fourth pin (PN4) and the fifth pin (PN4).

Abstract: A semiconductor device has: an inner active region 3 including a first electronic circuit formed on a semiconductor substrate; an outer active region 4 positioned between the edges 2a, 2b of the semiconductor substrate 2 and the inner active region 3 and including a second electronic circuit formed on the semiconductor substrate 2; a main bonding pad 6a for assembly formed inside a region where the inner active region 3 is opposed to the outer active region 4 and formed along the outer periphery of the inner active region 3; a sub-bonding pad 7 for analysis formed outside the opposing region 5 where the inner active region 3 is opposed to the outer active region 4; and a pad-to-pad interconnection wiring 8 for connecting the main bonding pad 6a to the sub-bonding pad 7.

Abstract: A semiconductor device has: an inner active region 3 including a first electronic circuit formed on a semiconductor substrate; an outer active region 4 positioned between the edges 2a, 2b of the semiconductor substrate 2 and the inner active region 3 and including a second electronic circuit formed on the semiconductor substrate 2; a main bonding pad 6a for assembly formed inside a region where the inner active region 3 is opposed to the outer active region 4 and formed along the outer periphery of the inner active region 3; a sub-bonding pad 7 for analysis formed outside the opposing region 5 where the inner active region 3 is opposed to the outer active region 4; and a pad-to-pad interconnection wiring 8 for connecting the main bonding pad 6a to the sub-bonding pad 7.

Abstract: In the memory access device, a memory address space of the RAM is divided into a plurality of blocks BK0 to BKn having continuous address areas. Address buses and data buses of the CPU and the RTD are connected to each of the blocks BK0 to BKn. The memory access control circuit checks whether memory blocks accessed by the CPU and the RTD are same. The memory access control circuit permits simultaneous access by the CPU and the RTD to the memory blocks when the memory block accessed by the CPU and the RTD are not same.

Abstract: There is provided a scan test system comprising: a semiconductor device including a scan register connected between an input/output pin on an analog input side and an internal system logic; a semiconductor device including a scan register connected between an input/output pin on an analog output side and an analog sensor; and an analog wiring connecting the input/output pins each other. Thus, the scan register can be chained to thereby constitute a boundary scan register chain, and thereby JTAG control can be carried out by use of TAPC. Therefore, monitoring inspection where probes are set up by means of high-density-assembling of semiconductor devices and the multiple pins of low-cost devices, can be achieved.

Abstract: A PLL circuit including multiple sets of phase locked loops, each of which has a phase comparator, a charge pump, a low pass filter, as oscillator, a clock generator and a frequency divider. The various oscillators of the multiple sets each have a different oscillation frequency. The clock generator generates a multiphase clock signal from a single phase clock signal generated by the oscillator. The PLL circuit generates multiple single phase clock signals and multiphase clock signals without need to tune the oscillation frequency of the VCOs over a wide range. The noise of the PLL is reduced since each VCO covers a smaller range of oscillation frequencies.

Abstract: An analog section (4) including the selector for analog input terminals, ladder resistors, a decoder for decoding the output of the ladder resistors, a chopper amplifier, and a sample and hold circuit, is operated by 5 V power-supply system. A digital section (5) that generates a control signal for controlling the operation of the analog section 4 is operated by 3.3 V power-supply system. No design change of a sensor connected from outside a microcomputer is required.

Abstract: A flash memory comprising a power supply controller and a second controller, as well as a microcomputer incorporating the flash memory. A power supply terminal of the power supply controller is furnished separately from a power supply terminal of those circuits in the second controller which operate on the same supply voltage as the power supply controller, whereby controlled voltages and ground potential are stabilized for the memory and microcomputer.

Abstract: There is provided an analog-to-digital converter comprising a first data register (4) for storing an m-bit analog-to-digital conversion result, a second data register (5) for storing an n-bit (n is smaller than m) analog-to-digital conversion result, and an analog-to-digital conversion control circuit (3) for transferring the n (n is smaller than m) highmost bits of the m-bit analog-to-digital conversion result stored in the first data register (4) as an n-bit analog-to-digital conversion result to the second data register (5).

Abstract: The invention provides a counting device and a direct memory access system using the counting device. In the counting device, a carry/borrow signal to be supplied from a predetermined one-bit counter among a plurality of one-bit counters to another one-bit counter in the subsequent stage is inputted to an input/cutoff element such as an AND circuit. The input/cutoff element is also supplied with a control signal for controlling the input/cutoff of the carry/borrow signal. Thus, the range of the values to be counted can be changed.

Abstract: An output control circuit capable of reducing a time lag at the time of switching connection of a flip-flop 3 and port latch 2, which output PWM waveforms, with an input/output terminal 5 to provide a more real-time control, and increasing the control accuracy, by setting data specifying a port latch 2 or flip-flop 3 which is a signal source to be connected next with an input/output terminal in an operation mode reload register 7 beforehand, and reloading the data directly to an operation mode register 4 by means of a reload signal RL.

Abstract: A matte film made of a composition comprising (a) from 3 to 20 parts by weight of a polyarylate resin made of terephthalic acid, isophthalic acid (the molar ratio of the terephthalic acid group to the isophthalic acid group being from 9:1 to 1:9) and a bivalent phenolic compound, (b) from 60 to 94 parts by weight of a linear polyester resin and (c) from 3 to 30 parts by weight of a styrene resin or an acrylic resin, and satisfying the following condition:A-10.ltoreq.S.ltoreq.A+15where A is the parts by weight of the polyarylate resin and S is the parts by weight of the styrene resin or acrylic resin, and said film being stretched at least 1.5 times in at least one direction.