Abstract: A semiconductor integrated circuit design support system having a partial power control mechanism includes a partial power control simulation program configured to perform a partial power control simulation on the basis of a circuit description of the semiconductor integrated circuit and a power specifications description, a power mode transition detection program configured to detect a power mode which is run during execution of the partial power control simulation and record power mode information of an examined power mode, and a power mode transition check program configured to check whether the examined power mode recorded at the time of execution of partial power control is used and output a check result.

Abstract: A semiconductor integrated circuit includes an adjuster and a controller. The adjuster adjusts transmission and reception of data by temporarily holding the data transmitted and received among a plurality of devices and output location information on the data. The controller controls power consumption of at least one of target devices based on a change amount of the location information.

Abstract: According to one embodiment, a verification device of semiconductor integrated circuit includes an assertion based verification unit, a logic generating unit, a signal restriction generating unit, and an estimation unit. The assertion based verification unit performs assertion based verification of the circuit description based on the assertion description, and generates pass information when the operation of the signal described in the assertion description conforming to a preliminary condition is observed in the circuit description, or generates failure information when the operation of the signal is not observed in the circuit description. The logic generating unit extracts a signal corresponding to the failure information from the assertion description, and generates an input/output logic of the circuit description from the extracted signal. The signal restriction generating unit generates a signal restriction based on the input/output logic.

Abstract: A semiconductor integrated circuit includes an adjuster and a controller. The adjuster adjusts transmission and reception of data by temporarily holding the data transmitted and received among a plurality of devices and output location information on the data. The controller controls power consumption of at least one of target devices based on a change amount of the location information.

Abstract: An apparatus for analyzing circuit specification description design has a circuit specification description inputting section that analyzes and obtains information of a related signal, information of the maximum number of cycles in the related signal, and a definite value in a site defined in the circuit specification description for the related signal contained in a circuit specification description, a data base generating section that generates signal variation data indicating time-series signal variation, wherein a definitive value is set in the site defined in the circuit specification description and a predetermined flag is set in a site where the value is not defined in the signal variation data, and a waveform diagram data outputting section that outputs waveform diagram data for displaying the time-series signal variation in a form of a waveform diagram on the basis of the definite value and the predetermined flag set in the data.

Abstract: A semiconductor integrated circuit design support system having a partial power control mechanism includes a partial power control simulation program configured to perform a partial power control simulation on the basis of a circuit description of the semiconductor integrated circuit and a power specifications description, a power mode transition detection program configured to detect a power mode which is run during execution of the partial power control simulation and record power mode information of an examined power mode, and a power mode transition check program configured to check whether the examined power mode recorded at the time of execution of partial power control is used and output a check result.

Abstract: It is a verification device of semiconductor integrated circuit configured to verify the equivalence of circuit description and assertion description.

Abstract: A method for supporting the register-transfer-level (RTL) design of a semiconductor integrated circuit, includes reading an RTL description related to the semiconductor integrated circuit into a first memory, the RTL description including a description of a compound block containing a mixture of combinational and non-combinational circuits, analyzing the RTL description, extracting a description of the non-combinational circuit from the compound block description, reading an RTL library into a second memory, comparing the logic of the extracted non-combinational circuit description with the logic of each cell of the RTL library, and in accordance with to a result of the comparison, replacing the extracted non-combinational circuit description with a cell of the RTL library having the same logic as the logic of the extracted non-combinational circuit description.

Abstract: An apparatus for analyzing circuit specification description design has a circuit specification description inputting section that analyzes and obtains information of a related signal, information of the maximum number of cycles in the related signal, and a definite value in a site defined in the circuit specification description for the related signal contained in a circuit specification description, a data base generating section that generates signal variation data indicating time-series signal variation, wherein a definitive value is set in the site defined in the circuit specification description and a predetermined flag is set in a site where the value is not defined in the signal variation data, and a waveform diagram data outputting section that outputs waveform diagram data for displaying the time-series signal variation in a form of a waveform diagram on the basis of the definite value and the predetermined flag set in the data.

Abstract: There is provided with a circuit design verification method including: accepting input of a circuit description which describes a circuit by using a plurality of conditional statements each including one or more conditional elements; extracting each conditional statement included in the circuit description and each conditional element included in the conditional statements; executing the circuit description by using test data for the circuit; and generating a table including verification information for each conditional statement, the verification information representing (A1) whether each conditional element has been always true, (A2) whether each conditional element has been always false, or (A3) whether each conditional element has been both true and false when the conditional statement is satisfied.

Abstract: An extractor extracts descriptions unexecuted in the logic simulation according to code coverage information for the circuit description. An examiner examines whether or not there is a possibility of executing the extracted unexecuted descriptions. A prohibited-input-checker generator generates a test pattern. The test pattern is to execute descriptions including unexecuted descriptions that there is a possibility of executing and excluding unexecuted descriptions that there is no possibility of executing as determined by the examiner. The prohibited-input-checker generator also generates a prohibited-input checker to check whether or not an input pattern of a logic simulation to be carried out is equal to an input pattern of the test pattern to execute the unexecuted description if the test bench is regarded as a prohibited input under a specification at a logic simulation using the test pattern to execute the unexecuted description.

Abstract: A method for supporting the register-transfer-level (RTL) design of a semiconductor integrated circuit, includes reading an RTL description related to the semiconductor integrated circuit into a first memory, the RTL description including a description of a compound block containing a mixture of combinational and non-combinational circuits, analyzing the RTL description, extracting a description of the non-combinational circuit from the compound block description, reading an RTL library into a second memory, comparing the logic of the extracted non-combinational circuit description with the logic of each cell of the RTL library, and in accordance with to a result of the comparison, replacing the extracted non-combinational circuit description with a cell of the RTL library having the same logic as the logic of the extracted non-combinational circuit description.

Abstract: A method for supporting the register-transfer-level (RTL) design of a semiconductor integrated circuit, includes reading an RTL description related to the semiconductor integrated circuit into a first memory, the RTL description including a description of a compound block containing a mixture of combinational and non-combinational circuits, analyzing the RTL description, extracting a description of the non-combinational circuit from the compound block description, reading an RTL library into a second memory, comparing the logic of the extracted non-combinational circuit description with the logic of each cell of the RTL library, and in accordance with to a result of the comparison, replacing the extracted non-combinational circuit description with a cell of the RTL library having the same logic as the logic of the extracted non-combinational circuit description.

Abstract: A circuit designing apparatus comprising: unit for specifying the changed points of the circuit description automatically in predetermined unit, and classifying the plural test vectors into those related with the changed points and others not; wherein the second and subsequent logic verification processes are executed by using only the test vectors relating to the changed points. As a result, the time required for circuit design can be substantially curtailed.

Abstract: A method for supporting the register-transfer-level (RTL) design of a semiconductor integrated circuit, includes reading an RTL description related to the semiconductor integrated circuit into a first memory, the RTL description including a description of a compound block containing a mixture of combinational and non-combinational circuits, analyzing the RTL description, extracting a description of the non-combinational circuit from the compound block description, reading an RTL library into a second memory, comparing the logic of the extracted non-combinational circuit description with the logic of each cell of the RTL library, and in accordance with to a result of the comparison, replacing the extracted non-combinational circuit description with a cell of the RTL library having the same logic as the logic of the extracted non-combinational circuit description.

Abstract: A method for supporting the register-transfer-level (RTL) design of a semiconductor integrated circuit, includes reading an RTL description related to the semiconductor integrated circuit into a first memory, the RTL description including a description of a compound block containing a mixture of combinational and non-combinational circuits, analyzing the RTL description, extracting a description of the non-combinational circuit from the compound block description, reading an RTL library into a second memory, comparing the logic of the extracted non-combinational circuit description with the logic of each cell of the RTL library, and in accordance with to a result of the comparison, replacing the extracted non-combinational circuit description with a cell of the RTL library having the same logic as the logic of the extracted non-combinational circuit description.

Abstract: A computer implemented method for design verification using logical simulation of a circuit description having a plurality of hierarchies from top to bottom in accordance with abstraction of circuit components, which have an arithmetic and logic function, reads the circuit description and analyzes signal connection topologies between the hierarchies of the circuit description from top to bottom. The method stores the data of the signal connection topologies. The method reads properties of target modules implemented by the circuit components in the circuit description. The method extracts a property part having a signal communicating between the target modules. The method extracts an output operation property, defining output operation of an output side module, and an expecting operation property, defining an expecting operation of an input side module among the properties of the target modules. The method compares the output operation properties with the expecting operation properties.

Abstract: A method for supporting the register-transfer-level (RTL) design of a semiconductor integrated circuit, includes reading an RTL description related to the semiconductor integrated circuit into a first memory, the RTL description including a description of a compound block containing a mixture of combinational and non-combinational circuits, analyzing the RTL description, extracting a description of the non-combinational circuit from the compound block description, reading an RTL library into a second memory, comparing the logic of the extracted non-combinational circuit description with the logic of each cell of the RTL library, and in accordance with to a result of the comparison, replacing the extracted non-combinational circuit description with a cell of the RTL library having the same logic as the logic of the extracted non-combinational circuit description.

Abstract: To provide a design verification device, a method and a memory medium therefor, for a semiconductor integrated circuit, capable of effectively introducing the formal verification in a higher-level design and capable of constructing a high-speed function verification environment with high verification assurance.

Abstract: A system for verifying a circuit represented with a circuit description including a plurality of descriptions, the system comprising a simulator configured to carry out a logic simulation of the circuit description with the use of a test bench for the circuit description, an extractor configured to extract descriptions unexecuted in the logic simulation according to code coverage information for the circuit description, an examiner configured to examine whether or not there is a possibility of executing the extracted unexecuted descriptions, and a prohibited-input-checker generator configured to generate an test pattern to execute the unexecuted description that there is a possibility of executing, and to generate a prohibited-input checker to check whether or not an input pattern of a logic simulation to be carried out is equal to an input pattern of the test pattern to execute the unexecuted description if the test bench is regard as a prohibited input under a specification at a logic simulation using the t