Abstract: An electromagnetic shield is disposed in front of a radar. The radar has different angles of view in different directions. The radar has a first angle of view in a first direction and a second angle of view in a second direction. The second angle of view is smaller than the first angle of view. The second direction is orthogonal to the first direction. The electromagnetic shield has a pair of first sides and a pair of second sides. The pair of first sides face each other in the first direction. The pair of second sides face each other in the second direction. The electromagnetic shield includes a dielectric. At least one of the pair of first sides includes a structure having at least one selected from the group consisting of a projecting portion and a recessed portion.

Abstract: An electromagnetic shield includes a plate-shaped base, a plurality of first projecting portions, and a contact portion. The base has a first surface and a second surface. The first surface is a surface configured to allow an electromagnetic wave to be incident on the first surface. The second surface is distant from the first surface. The plurality of first projecting portions project from the first surface in a direction away from the second surface. The electromagnetic shield is capable of being attached to a component such that the component is in contact with the contact portion and the first surface faces the component. A distance from the contact portion to the particular portion in a direction parallel to the first surface is equal to or shorter than a first distance d1 between the first projecting portion closest to the contact portion and the contact portion.

Abstract: An electromagnetic shield includes a plate-shaped base, a plurality of first projecting portions, and a plurality of second projecting portions. The plate-shaped base has a first surface and a second surface. The first surface is a surface configured to allow an electromagnetic wave Ei to be incident on the first surface. The second surface is a surface being distant from the first surface and extending along the first surface. The plurality of first projecting portions project from the first surface in a direction away from the second surface. The plurality of second projecting portions project from the second surface in a direction away from the first surface. The electromagnetic shield includes a dielectric.

Abstract: The present invention provides a member which, with a novel configuration, can transmit and attenuate incident radio waves, without the need for mixing a radio wave absorption material for example a dielectric loss material such as carbon particles or a magnetic loss material such as an iron oxide powder, or incorporating a scattering body. Provided is a radio wave scattering body that is characterized by being configured to transmit at least a portion of incident radio waves and to emit the transmitted radio waves in a scattering state, and comprising a resin composition in which a resin is a main component.

Abstract: A PLL frequency synthesizer, which comprises a voltage controlled oscillator, and a comparison frequency divider for dividing a frequency of the output signal from the voltage controlled oscillator to output a comparison signal. A phase comparator in the synthesizer compares a phase of a reference signal to be fed thereto with a phase of the comparison signal, and generates first and second phase difference signals, based on the compared result. The synthesizer further includes a charge-pump circuit operated based on the first and second phase difference signals, and having an output terminal connected to the voltage controlled oscillator. The charge-pump circuit includes a first bipolar transistor connected between a high-potential power supply and the output terminal, and a second bipolar transistor connected between a low-potential power supply and the output terminal. The first and second bipolar transistors are controlled based on the first and second phase difference signals, respectively.

Abstract: A reference frequency divider divides a clock signal into a reference frequency signal, and outputs it. A comparison frequency divider circuit divides an output signal from a voltage controlled oscillator, and outputs it as a comparison signal. The reference signal and comparison signal are coupled to a phase comparator. The phase comparator detects the phase difference between the reference signal and comparison signal, and outputs a phase difference signal. A charge pump outputs a voltage signal in response to the phase difference signal from the phase comparator. A low pass filter smooths out the voltage signal from the charge pump to remove the high frequency components, and outputs a controlled voltage signal. A voltage controlled oscillator outputs an output signal with the frequency relating to the voltage value of the controlled voltage signal from the low pass filter. A frequency difference determining circuit compares the reference signal with the comparison signal.

Abstract: A level conversion circuit includes an ECL logic circuit including a current switch circuit having first and second transistors, each of the transistors having an emitter coupled to each other and at least one thereof receiving an input signal of ECL logic level, and an output transistor coupled to a collector of at least one of the first and second transistors; a current control circuit including a current mirror circuit having third and fourth transistors, at least one of the transistors being coupled to an output end of the output transistor, and controlling a current flowing through the output to thereby carry out a level conversion of a signal at the output end; and a switch circuit operative coupled to the current control circuit. The switch circuit responds to a control signal and thus controls a supply of a current or a break thereof from the output transistor to the current control circuit.

Abstract: A PLL frequency synthesizer includes a reset circuit which determines whether or not an oscillator starts to normally generate an oscillation signal in response to a power save signal which intermittently operates the oscillator in a standby mode and which outputs a reset signal to a prescaler when it is determined that the oscillator normally generates the oscillation signal. A hold circuit prevents a frequency-divided signal being output from the prescaler to a programmable counter and an initial phase detection circuit until the prescaler is reset to an initial state in response to the reset signal and starts to normally generate the frequency-divided signal.

Abstract: A PLL synthesizer includes a voltage-controlled oscillator generating an output signal having a frequency based on a first signal supplied thereto, a PLL control circuit which generates a second signal based on the output signal and a set frequency, a lowpass filter having an input terminal and an output terminal, for filtering the second signal supplied through the input terminal to thereby generate the first signal supplied to the voltage-controlled oscillator through the output terminal, and a switch circuit which is coupled between the input and output terminals of the lowpass filter and which supplies the second signal directly to the voltage-controlled oscillator during a predetermined time when the set frequency is changed.

Abstract: A semiconductor integrated circuit includes a logic circuit which has first and second transistors constituting an emitter coupled transistor pair and a third transistor which is used as a constant current source, a bias circuit which includes a fourth transistor having an emitter from which a first predetermined voltage is supplied to a base of the third transistor and an impedance having one end coupled to a first power source and another end coupled to a base of the fourth transistor to supply a second predetermined voltage thereto, and a clamping circuit. The clamping circuit is OFF and does not perform a clamping operation with respect to the base of the fourth transistor when the entire semiconductor integrated circuit needs to operate. When the entire semiconductor integrated circuit does not need to operate, the clamping circuit is ON to clamp the base potential of the fourth transistor so as to reduce the power consumption of the semiconductor integrate circuit.

Abstract: A latch circuit inputting and holding a write data including a data input terminal for receiving a write data signal and a feedback input terminal for receiving a feedback signal from an output terminal, the latch circuit through a feedback loop, wherein the output terminal of the latch circuit outputs the write data signal at a suitable timing. The latch circuit is operated such that a potential difference between a peak voltage of a logic amplitude and a reference voltage at the side at which the feedback signal is applied is set larger than a potential difference between the peak voltage of the logic amplitude and the reference voltage at the side at which the write data signal is applied.

Abstract: A master-slice-type semiconductor integrated circuit device including basic cells, each having at least one logical circuit element, and current source cells for supplying current to the basic cells, each having at least one current source element and separated from the basic cells. A logic circuit operatively connects at least one logical circuit element in one of the basic cells and at least one current source element in one of the current source cells. The basic cells are arranged in groups extending in a lateral direction of the device and form cell rows in the lateral direction with groups of current source cells periodically formed in each cell row. The groups of current source cells in different cells rows are aligned in a longitudinal direction perpendicular to the lateral direction. The logic circuit is connected by conductive strips formed in wiring channels, each wiring channel being formed parallel and adjacent to at least one cell row.

Abstract: A gate circuit device of an integrated circuit tester, for variably setting the signal propagation delay time of various integrated circuits to be tested at a predetermined value, includes a gate circuit having a pair of emitter coupled transistors and a constant current source transistor connected to the emitter side of the pair of transistors, and a terminal to apply a predetermined level of voltage to the base of the constant current source transistor to control the constant current. In addition to this manner of the voltage control of signal propagation delay time, a current adjustment circuit is utilized to generate current in a constant current source transistor in response to the control current. Thus, the gate circuit device controls the signal propagation delay time by regulating either voltage or current in response to the control current.

Abstract: A TTL circuit including an input circuit, an output circuit, elements for controlling the output circuit, and elements for delaying the operation of the controlling elements immediately after the voltage supply is turned on. The output of the TTL circuit is maintained at on "H" level until the voltage supply rises up to a predetermined level.

Abstract: A semiconductor device is used, for example, for controlling and driving thermal heads of a facsimile apparatus and includes a first circuit activated when power is supplied to the semiconductor device and a second circuit activated only when both power and a power control signal are applied to the semiconductor device. The semiconductor device further includes a power switch circuit which includes a semiconductor electronic circuit and which supplies power to the second circuit only when the power control signal is applied thereto.