Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.

Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.

Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.

Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is in contact with the P?-type impurity region and the gate insulating film, and an N??-type impurity region that surrounds at least a portion of the N?-type impurity region in plan view.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the P-well so as to extend under the pinning layer and the P?-type impurity region and be in contact with the P?-type impurity region and the gate insulating film, and an N+-type impurity region that is located in the P-well and includes a portion that is under a second end portion of the gate electrode.

Abstract: A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 ?m or more, the thickness of the second insulation layer is less than or equal to ? of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.

Abstract: A solid state imaging device according to the invention includes: a semiconductor layer of a first conductivity type; a gate insulation film that is located on the semiconductor layer; a gate electrode that is located on the gate insulation film; a first impurity region of a second conductivity type that is located at least in a region outside the gate electrode on a first end portion side; a second impurity region of the second conductivity type that is located in a region extending across a second end portion that is opposite to the first end portion of the gate electrode; and a third impurity region of the first conductivity type that is located on top of the second impurity region at a position outside the gate electrode on the second end portion side, and is in contact with the second impurity region.

Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.

Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.

Abstract: A solid state imaging element according to the invention includes: a semiconductor layer of a first conductivity type; a gate insulation film on the semiconductor layer; a gate electrode on the gate insulation film; a first impurity region of a second conductivity type in the semiconductor layer and in a region outside the gate electrode on a first end portion side; a second impurity region of the second conductivity type in the semiconductor layer and in a region outside the gate electrode on a second end portion side that is opposite to the first end portion of the gate electrode; and a third impurity region of the first conductivity type over the second impurity region in the semiconductor layer at a position separate from the second end portion of the gate electrode as viewed in plan view, and is in contact with the second impurity region.

Abstract: A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 ?m or more, the thickness of the second insulation layer is less than or equal to ? of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.

Abstract: The present invention provides a connection unit capable of accommodating nuts and showing sealing ability in a state installed on a housing. A connection unit S includes: a terminal block 100 having holes h3 at one side of for accommodating nuts n; a terminal-connecting portions 200 at least partially exposed when viewed from the other side and fixed to the terminal block 100 with the circumferences of the terminal-connecting portions 200 in tight contact with the terminal block 100; and a nut cover 300 for covering the nuts accommodated in the holes h3 for preventing the nuts n from coming off. The connection unit S further includes: guide grooves and guide ribs for restricting movement of the nut cover 300 relative to the terminal block 100; and locking hooks 116 and locking holes h5 for restricting movement of the nut cover 300 relative to the terminal block 100.

Abstract: A solid state imaging device according to the invention includes: a semiconductor layer of a first conductivity type; a gate insulation film that is located on the semiconductor layer; a gate electrode that is located on the gate insulation film; a first impurity region of a second conductivity type that is located at least in a region outside the gate electrode on a first end portion side; a second impurity region of the second conductivity type that is located in a region extending across a second end portion that is opposite to the first end portion of the gate electrode; and a third impurity region of the first conductivity type that is located on top of the second impurity region at a position outside the gate electrode on the second end portion side, and is in contact with the second impurity region.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the semiconductor layer under the P?-type impurity region and includes a portion that is under the pinning layer, and an N?-type impurity region that is in contact with the gate insulating film and the P?-type impurity region and is located so as to surround the N?-type impurity region in plan view.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the P-well so as to extend under the pinning layer and the P?-type impurity region and be in contact with the P?-type impurity region and the gate insulating film, and an N+-type impurity region that is located in the P-well and includes a portion that is under a second end portion of the gate electrode.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is in contact with the P?-type impurity region and the gate insulating film, and an N??-type impurity region that surrounds at least a portion of the N?-type impurity region in plan view.

Abstract: A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P?-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N?-type impurity region that is located in the semiconductor layer under the P?-type impurity region and includes a portion that is under the pinning layer, and an N?-type impurity region that is in contact with the gate insulating film and the P?-type impurity region and is located so as to surround the N?-type impurity region in plan view.

Abstract: An arrangement structure includes: a motor including: a motor main body including a stator and a rotor, the rotor being disposed to be rotatable relative to the stator; a case member configured to store the motor main body; and a connecting conductor configured to electrically connect an inside conductor disposed inside the case member and an outside conductor disposed outside the case member; and a support device fixed to the case member and a frame member of a vehicle, the support device being configured to support the motor on the frame member, wherein the connecting conductor is arranged directly below a fixing portion where the support device is fixed to the case member.

Abstract: The present invention provides a connection unit capable of accommodating nuts and showing sealing ability in a state installed on a housing. A connection unit S includes: a terminal block 100 having holes h3 at one side of for accommodating nuts n; a terminal-connecting portions 200 at least partially exposed when viewed from the other side and fixed to the terminal block 100 with the circumferences of the terminal-connecting portions 200 in tight contact with the terminal block 100; and a nut cover 300 for covering the nuts accommodated in the holes h3 for preventing the nuts n from coming off. The connection unit S further includes: guide grooves and guide ribs for restricting movement of the nut cover 300 relative to the terminal block 100; and locking hooks 116 and locking holes h5 for restricting movement of the nut cover 300 relative to the terminal block 100.