Abstract: A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

Abstract: A semiconductor memory device includes a plurality of memory cells, a memory cell array, bit lines, word lines, select gate lines, a column decoder, a first row decoder, a second row decoder, and first metal wiring. The memory cell includes a first MOS transistor with a charge accumulation layer and a control gate and a second MOS transistor connected to the first MOS transistor. The memory cell array has the memory cells arranged in a matrix. The word line connects commonly the control gates in the same row. The select gate line connects commonly the gates of the second MOS transistors in the same row. The first metal wiring layers are provided for every select gate lines, and pass through almost the central part of the memory cells. The first metal wiring layer is connected electrically to one of the select gate lines.

Abstract: A semiconductor memory system comprises a nonvolatile memory and a controller configured to control the nonvolatile memory. The controller causes management data for page data to be inputted to a redundant area of the nonvolatile memory before the execution of a program and, when moving the page data in the nonvolatile memory to one other page, controls the reading of the page data to check the page data for errors during a program period for the one other page.

Abstract: A semiconductor memory system having a nonvolatile memory and a controller configured to control the nonvolatile memory. The controller causes management data for page data to be inputted to a redundant area of the nonvolatile memory before the execution of a program and, when moving the page data in the nonvolatile memory to one other page, controls the reading of the page data to check the page data for errors during a program period for the one other page.

Abstract: A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing addresses of the defect cell and being arranged in a region along any edge of the semiconductor chip, and on the outside of the logic circuit unit, the memory macro unit and the electrode pad rows. Here, the logic circuit unit, the memory macro unit, the electrode pad rows and the fuse unit group are positioned on a semiconductor chip surface.

Abstract: A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing addresses of the defect cell and being arranged in a region along any edge of the semiconductor chip, and on the outside of the logic circuit unit, the memory macro unit and the electrode pad rows. Here, the logic circuit unit, the memory macro unit, the electrode pad rows and the fuse unit group are positioned on a semiconductor chip surface.

Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first and second MOS transistors. The first MOS transistor has a charge accumulation layer and a control gate. The second MOS transistor has one end of its current path connected to one end of a current path of the first MOS transistor. The local bit line connects other end of the current paths of the first MOS transistors. The first switch element makes a connection between the local bit lines and the global bit line. The holding circuit is connected to the global bit line and holds data to be written into the memory cells.

Abstract: A semiconductor memory device includes a plurality of memory cells, a memory cell array, bit lines, word lines, select gate lines, a column decoder, a first row decoder, a second row decoder, and first metal wiring. The memory cell includes a first MOS transistor with a charge accumulation layer and a control gate and a second MOS transistor connected to the first MOS transistor. The memory cell array has the memory cells arranged in a matrix. The word line connects commonly the control gates in the same row. The select gate line connects commonly the gates of the second MOS transistors in the same row. The first metal wiring layers are provided for every select gate lines, and pass through almost the central part of the memory cells. The first metal wiring layer is connected electrically to one of the select gate lines.

Abstract: A motor driven compressor having a motor for driving a compression mechanism includes a connecting portion for connecting between an external terminal for supplying electricity to the motor and a wire end portion of a stator of the motor. The connecting portion is located above the motor and the compression mechanism. Further, the connecting portion is formed on the stator housing which accommodates the motor and the stator. The connecting portion is disposed in a hollow projection portion, which extends upward from the housing. Accordingly, the motor driven compressor which is readily manufactured, may avoid a leakage current by insulating a terminal portion of the motor from the housing of compressor.

Abstract: A vibration type compressor related to the present invention, in which a compressor main body 3 is built into a gastight vessel 2 including a yoke 7-1, a magnetic path member 7 formed from a column-shaped core pole 7-2, a permanent magnet 12 arranged in the magnetic path, an electromagnetic coil 14 which is arranged within an annular magnetic gap 13 between the magnetic path members 7 by being supported by a mechanical vibration system to as to be able to vibrate and is wound around a lead plate to perform the connection treatment of a terminal thereof, a piston 16 connected to the electromagnetic coil 14, and a cylinder block 8 which closes the yoke 7-1 and in the interior of which is formed the cylinder portion 17 housing the piston 16, characterized in that the permanent magnet 12 is formed from a neodymium magnet or a rare-earth magnet and in that the cylindrical permanent magnet 12 is divided into four parts in the axial direction thereof, the four-part divided magnet being bonded and fixed to the side o

Abstract: A semiconductor memory system comprises a nonvolatile memory and a controller configured to control the nonvolatile memory. The controller causes management data for page data to be inputted to a redundant area of the nonvolatile memory before the execution of a program and, when moving the page data in the nonvolatile memory to one other page, controls the reading of the page data to check the page data for errors during a program period for the one other page.

Abstract: A fuse circuit 1 comprises an electrically programmable fuse 10 and a data latch circuit 11 to hold programmed fuse data. In the data latch circuit 11, prior to programming, a node FUADD is precharged to “H” by a precharge circuit 14 and preset at “H” as the result of the logical product of a fail address FAADD and a latch signal LATCHp by a preset circuit 12 when the fuse 10 needs to be programmed. A programming selecting circuit 13 monitors the node FUADD to select whether to perform or not to performance the programming of the fuse 10. Accordingly, efficient electric programming control becomes possible without using a dedicated register to hold a fuse address to be programmed.

Abstract: A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing addresses of the defect cell and being arranged in a region along any edge of the semiconductor chip, and on the outside of the logic circuit unit, the memory macro unit and the electrode pad rows. Here, the logic circuit unit, the memory macro unit, the electrode pad rows and the fuse unit group are positioned on a semiconductor chip surface.

Abstract: A fuse circuit 1 comprises an electrically programmable fuse 10 and a data latch circuit 11 to hold programmed fuse data. In the data latch circuit 11, prior to programming, a node FUADD is precharged to “H” by a precharge circuit 14 and preset at “H” as the result of the logical product of a fail address FAADD and a latch signal LATCHp by a preset circuit 12 when the fuse 10 needs to be programmed. A programming selecting circuit 13 monitors the node FUADD to select whether to perform or not to performance the programming of the fuse 10. Accordingly, efficient electric programming control becomes possible without using a dedicated register to hold a fuse address to be programmed.

Abstract: A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE<ICB according to a voltage applied across a base and emitter where IBE is the base current flowing through a base-emitter path in a forward direction, and ICB is the base current flowing through a collector-base path in a reverse direction.

Abstract: A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE<ICB according to a voltage applied across a base and emitter where IBE is the base current flowing through a base-emitter path in a forward direction, and ICB is the base current flowing through a collector-base path in a reverse direction.

Abstract: A semiconductor storage apparatus having a plurality of memory-cells arranged, forming array which is composed of regular memory-cell blocks and redundant memory-cell blocks, wherein grouping of each of a regular memory-cell blocks each having one DQ line in the form of an overlaid structure is changed in accordance with the addresses of the defective column in a data line, the redundant memory-cell blocks are grouped in accordance with the changed groups of the regular memory-cell blocks, and the grouped redundant memory-cell blocks corresponding to the changed group of the regular memory-cell blocks replaces the regular memory-cell blocks including the defective cell.

Abstract: When a clock enable signal asynchronous with a clock signal is set at a high level, a power-down control circuit sets a power-down signal at a high level to release a power-down mode. When the power-down mode is released, a clock control circuit outputs an internal clock signal such that an output signal of a command decoder can be latched. According to such a constitution, a period of time from the latching of the command after releasing the power-down mode to the time when the command can be transferred will be reduced, and a high-speed operation can be attained.

Abstract: A sense amplifier is connected between memory cell arrays, a re-writing register is arranged adjacent to the sense amplifier, first transfer gates are disposed between the sense amplifier and the memory cell arrays, second transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.

Abstract: A semiconductor device includes a memory cell array having memory cells arranged in a matrix form, a plurality of bit lines for communicating information to the memory cells, and a plurality of word lines crossing the bit lines to select among the memory cells, a plurality of sense amplifiers for amplifying data read out onto the bit lines, a plurality of data lines for transferring data amplified by the sense amplifiers to the outside of the cell array, the plurality of data lines including first and second wiring layers, a plurality of column select circuits for controlling connections of the plurality of data lines and the plurality of sense amplifiers, and a plurality of control signal lines connected to the plurality of column select circuits, the plurality of control lines including third and fourth wiring layers.