Patents by Inventor Takehiro Hisatomi

Takehiro Hisatomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100052093
    Abstract: A semiconductor substrate is a semiconductor substrate used when an SOI substrate having an SOI structure is manufactured, in which a silicon oxide film and a silicon single crystal layer are formed on the surface of a silicon substrate. A region containing no nitrogen, which is made of a silicon single crystal layer with a thickness of 10 ?m or less, is formed in the vicinity of the surface, and the nitrogen concentration of a portion excluding the region, that is, the region containing nitrogen, is in a range of 1×1013 to 5×1015 atoms/cm3.
    Type: Application
    Filed: August 27, 2009
    Publication date: March 4, 2010
    Applicant: SUMCO CORPORATION
    Inventor: Takehiro HISATOMI
  • Patent number: 6074479
    Abstract: This invention anneals a vertical stack of two or more groups of unseparated wafers, with approximately 10 wafers in each group. The invention makes it possible to anneal more wafers in a single annealing operation under a variety of conditions, including: oxygen outer diffusion annealing to form a denuded zone; annealing to control bulk micro defects and provide intrinsic gettering functions; annealing to enhance gate oxide integrity by eliminating crystal-originated particles from the wafer surface and internal grown-in or as-grown defects; and suppression of dislocation and slip in elevated temperature environments.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: June 13, 2000
    Assignee: Sumitomo Metal Industries Ltd.
    Inventors: Naoshi Adachi, Takehiro Hisatomi, Masakazu Sano
  • Patent number: 5931662
    Abstract: The present invention is designed to provide an annealing method for silicon single crystal wafers, which makes it possible to increase the number of silicon single crystal wafers processed during a single annealing process under a variety of annealing performed on silicon single crystal wafers, such as oxygen outer diffusion annealing for forming a DZ layer, annealing that generates and controls BMD for providing IG functions, and annealing that endeavors to improve and enhance GOI characteristics by eliminating wafer surface layer COP, and internal grown-in defects, and also enables the suppression of dislocation and slip in elevated temperature annealing environments. It calls for annealing to be performed by stacking up around 10 wafers, treating this group as a unit, placing this group, either horizontally or slightly inclined at an angle of roughly 0.5.about.5.degree.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: August 3, 1999
    Assignee: Sumitomo Sitix Corporation
    Inventors: Naoshi Adachi, Takehiro Hisatomi, Masakazu Sano