Abstract: A semiconductor storage apparatus and an error checking and correction (ECC) related information reading method, which can output various information related to pages that have been error-corrected during a continuous reading operation, are provided. A NAND flash memory includes a memory cell array, a continuous reading component, an ECC related information memory part, and an output component. The continuous reading component continuously reads pages of the memory cell array. The ECC related information memory part stores page addresses of all of the pages that have been error-corrected by an ECC circuit regarding the pages continuously read by the continuous reading component. The output component outputs page addresses stored in the ECC related information memory part in response to a read command after the continuous reading operation.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a page-reading portion which selects a page of the memory cell array, reads data of the selected page, and transmits the read data to a data-holding portion, and a control portion which controls continuous reading of pages. When a command related to termination of the continuous reading is input, the control portion terminates the continuous reading. When the command related to the termination of the continuous reading is not input, the continuous reading terminates. During a period in which the continuous reading is performed continuously, even if a chip selection signal is toggled, the continuous reading can be performed continuously without inputting a page-data read command.

Abstract: A semiconductor storage device and a memory system having the same. The semiconductor storage device includes a memory array, an error checking/correction (ECC) element, and a setting element. The ECC element stores generated error correction codes to a storage area. The setting element can set the storage area from the external.

Abstract: A semiconductor memory device, a flash memory and a continuous reading method thereof are provided for achieving a continuous reading of pages in high speed. A flash memory of the invention includes a memory cell array; a page reading element, which selects a page of the memory cell array and reads out data of the selected page to a page buffer/sense circuit; a page information storage element, which stores page information related to a range of a continuous reading; and a control element, which controls the continuous reading of the page. The control element determines whether to resume the continuous reading according to the page information. When it is determined to resume the continuous reading, the continuous reading can still be performed without a page data read command and a page address being inputted even if a chip select signal is toggled.

Abstract: The invention provides a flash memory which may effectively protect information with a high security level. A flash memory includes a setting part. When the setting part is inputted a specific command, the setting part sets up specific address information to a nonvolatile configuration register, and sets up specific data in a hidden storage region. The flash memory also includes: a comparing part, which compares inputted address information and the specific address information during a reading operation; and a control part, which reads specific data set in the storage region and erases a specific address when two address information are consistent, and reads data stored in a memory array according to the inputted address information when two address information are inconsistent.

Abstract: A semiconductor memory device, a flash memory and a continuous reading method thereof are provided for achieving a continuous reading of pages in high speed. A flash memory 100 of the invention includes a memory cell array 110; a page reading element, which selects a page of the memory cell array 110 and reads out data of the selected page to a page buffer/sense circuit 180; a page information storage element 160, which stores page information related to a range of a continuous reading; and a control element 150, which controls the continuous reading of the page. The control element 150 determines whether to resume the continuous reading according to the page information. When it is determined to resume the continuous reading, the continuous reading can still be performed without a page data read command and a page address being inputted even if a chip select signal is toggled.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a page-reading portion which selects a page of the memory cell array, reads data of the selected page, and transmits the read data to a data-holding portion, and a control portion which controls continuous reading of pages. When a command related to termination of the continuous reading is input, the control portion terminates the continuous reading. When the command related to the termination of the continuous reading is not input, the continuous reading terminates. During a period in which the continuous reading is performed continuously, even if a chip selection signal is toggled, the continuous reading can be performed continuously without inputting a page-data read command.

Abstract: A semiconductor storage device and a memory system having the same. The semiconductor storage device includes a memory array, an error checking/correction (ECC) element, and a setting element. The ECC element stores generated error correction codes to a storage area. The setting element can set the storage area from the external.

Abstract: A semiconductor memory device includes a memory array, a setting unit and a control unit. The memory array consists of non-volatile memory cells. The setting unit set a page address of the memory array which is initially read out at startup. The control unit performs an internal sequence to read out the page address from the setting unit at startup and, according to the read-out page address, transmits page data corresponding to the read-out page address from the memory array to a page buffer.

Abstract: The invention provides a flash memory which may effectively protect information with a high security level. A flash memory includes a setting part. When the setting part is inputted a specific command, the setting part sets up specific address information to a nonvolatile configuration register, and sets up specific data in a hidden storage region. The flash memory also includes: a comparing part, which compares inputted address information and the specific address information during a reading operation; and a control part, which reads specific data set in the storage region and erases a specific address when two address information are consistent, and reads data stored in a memory array according to the inputted address information when two address information are inconsistent.

Abstract: A semiconductor memory device includes a memory array, a setting unit and a control unit. The memory array consists of non-volatile memory cells. The setting unit set a page address of the memory array which is initially read out at startup. The control unit performs an internal sequence to read out the page address from the setting unit at startup and, according to the read-out page address, transmits page data corresponding to the read-out page address from the memory array to a page buffer.

Abstract: A non-volatile semiconductor memory is provided, including a memory array having a first and a second memory planes, a page buffer, holding data transmitted by pages selected by address information from a memory array; data register, capable of serially outputting data received by the page buffer according to a clock signal. The pages selected by the first and the second memory planes are simultaneously transmitted to the page buffer. The data reading includes: transmitting the data of the second page of the second memory plane from the page buffer to the data register when the data of the first page of the first memory plane is outputted from the data register; transmitting the data of the second page of the first memory plane from the page buffer to the data register when the data of the second page of the second memory plane is outputted from the data register.