Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a silicon pattern for a fuse element, a metal silicide layer formed on an upper surface and a side surface of the silicon pattern, a gate electrode for MISFET, and a metal silicide layer formed on an upper surface of the gate electrode. The height from the lower surface of the silicon pattern to the lower end of the metal silicide layer is lower than the height from the lower surface of the gate electrode to the lower end of the metal silicide layer.

Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a silicon pattern for a fuse element, a metal silicide layer formed on an upper surface and a side surface of the silicon pattern, a gate electrode for MISFET, and a metal silicide layer formed on an upper surface of the gate electrode. The height from the lower surface of the silicon pattern to the lower end of the metal silicide layer is lower than the height from the lower surface of the gate electrode to the lower end of the metal silicide layer.

Abstract: A compound of the formula (I): wherein R1 is hydrogen, halogen, carbamoyl, cyano, formyl, or lower alkyl optionally substituted with halogen, amino or a protected amino; R2 is hydrogen, halogen, cyano or lower alkoxy; R3 is phenyl or pyridyl, each of which is substituted with lower alkoxy; and R4 is lower alkoxy; provided that either R1 or R2 is hydrogen, then the other is other than hydrogen, or its salts, which are useful as a medicament.

Abstract: A test apparatus includes a plurality of test circuits, each test circuit having a connection section to be used for connecting a semiconductor device under test (DUT), such as DRAM; a driver circuit for sending a write signal to the connection section in response to a test pattern output from a test pattern generator; a timer for setting a pause time and read time of the DUT; a determination circuit which is connected to the connection section, determines whether the DUT is defective or acceptable in accordance with the level of a signal read from the semiconductor storage device, and transmits a result of determination to a result processing circuit; and a counter for controlling operation of the driver circuit and operation of the determination circuit in response to the test pattern. The apparatus simultaneously tests a plurality of semiconductor storage devices under test connected to the connection sections of the respective test circuits.

Abstract: A compound of the formula (I), wherein R1 is hydrogen, halogen, carbymoyl, cyano, formuly, or lower alkyl optionally substituted with halogen, amino or a protected amino, R2 is hydrogen, halogen, cyano or lower alkoxy, R3 is phenyl or pyridyl, each of which is substituted with lower alkoxy, and R4 is lower alkoxy; provided that either R1 or R2 is hydrogen, then the other is other than hydrogen, or its salts, which are useful as a medicament.

Abstract: A switching circuit between a main circuit and a redundant circuit in a semiconductor device is disclosed. The redundant circuit replaces the main circuit by blowing a fuse. But a nullifying means can nullify blowing of the fuse, if needed. A switching element connected in parallel with the fuse and a control means enable nullification. The control means turn on the switching element to ascertain whether nullification is effective, and fix the nullification by blowing a fuse in the control means.

Abstract: A switching circuit between a main circuit and a redundant circuit in a semiconductor device is disclosed. The redundant circuit replaces the main circuit by blowing a fuse. But a nullifying means can nullify blowing of the fuse, if needed. A switching element connected in parallel with the fuse and a control means enable nullification. The control means turn on the switching element to ascertain whether nullification is effective, and fix the nullification by blowing a fuse in the control means.

Abstract: A redundancy row decoder in a DRAM includes a plurality of N channel MOS transistors connected in series between one terminal of each fuse and a line of a ground potential, the plurality of N channel MOS transistors having their gates receiving a predecode signal allocated to a corresponding word line. As compared with a conventional case where only one N channel MOS transistor is connected between one terminal of each fuse and the line of the ground potential, leakage current flowing through each fuse is made smaller.

Abstract: A redundancy row decoder in a DRAM includes a plurality of N channel MOS transistors connected in series between one terminal of each fuse and a line of a ground potential, the plurality of N channel MOS transistors having their gates receiving a predecode signal allocated to a corresponding word line. As compared with a conventional case where only one N channel MOS transistor is connected between one terminal of each fuse and the line of the ground potential, leakage current flowing through each fuse is made smaller.