Patents by Inventor Takehiro OURA

Takehiro OURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10153216
    Abstract: Degradation of reliability of a semiconductor device is prevented. An electrode pad included mainly of aluminum is formed over amain surface of a semiconductor wafer. Subsequently, a first insulating member and a second insulating member are formed over the main surface of the semiconductor wafer so as to cover the electrode pad, and thereafter an opening portion that exposes a surface of the electrode pad is formed in the first insulating member and the second insulating member by a dry etching method using an etching gas including a halogen-based gas. Thereafter, an oxide film with a thickness of 2 nm to 6 nm is formed over the exposed surface of the electrode pad by performing a heat treatment at 200° C. to 300° C. in an air atmosphere, and then the semiconductor wafer is stored.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Oura
  • Publication number: 20180033702
    Abstract: Degradation of reliability of a semiconductor device is prevented. An electrode pad included mainly of aluminum is formed over amain surface of a semiconductor wafer. Subsequently, a first insulating member and a second insulating member are formed over the main surface of the semiconductor wafer so as to cover the electrode pad, and thereafter an opening portion that exposes a surface of the electrode pad is formed in the first insulating member and the second insulating member by a dry etching method using an etching gas including a halogen-based gas. Thereafter, an oxide film with a thickness of 2 nm to 6 nm is formed over the exposed surface of the electrode pad by performing a heat treatment at 200° C. to 300° C. in an air atmosphere, and then the semiconductor wafer is stored.
    Type: Application
    Filed: September 29, 2017
    Publication date: February 1, 2018
    Inventor: Takehiro OURA
  • Patent number: 9799572
    Abstract: Degradation of reliability of a semiconductor device is prevented. An electrode pad included mainly of aluminum is formed over a main surface of a semiconductor wafer. Subsequently, a first insulating member and a second insulating member are formed over the main surface of the semiconductor wafer so as to cover the electrode pad, and thereafter an opening portion that exposes a surface of the electrode pad is formed in the first insulating member and the second insulating member by a dry etching method using an etching gas including a halogen-based gas. Thereafter, an oxide film with a thickness of 2 nm to 6 nm is formed over the exposed surface of the electrode pad by performing a heat treatment at 200° C. to 300° C. in an air atmosphere, and then the semiconductor wafer is stored.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: October 24, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro Oura
  • Patent number: 9786630
    Abstract: A semiconductor device manufacturing method improves the yield of manufacturing semiconductor devices. There are provided an insulating film for covering multiple bonding pads, a first protective film over the insulating film, and a second protective film over the first protective film. In semiconductor chips, multiple electrode layers are coupled electrically to each of the bonding pads via first openings formed in the insulating film and second openings formed in the first protective film. Multiple bump electrodes are coupled electrically to each of the electrode layers via third openings formed in the second protective film. In pseudo chips, the second openings are formed in the first protective film and the third openings are formed in the second protective film. The insulating film is exposed at the bottom of the second openings coinciding with the third openings. A protective tape is applied to a principal plane to cover the bump electrodes.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 10, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Ota, Kentaro Kita, Takehiro Oura, Kohei Yoshida
  • Publication number: 20170186725
    Abstract: A semiconductor device manufacturing method improves the yield of manufacturing semiconductor devices. There are provided an insulating film for covering multiple bonding pads, a first protective film over the insulating film, and a second protective film over the first protective film. In semiconductor chips, multiple electrode layers are coupled electrically to each of the bonding pads via first openings formed in the insulating film and second openings formed in the first protective film. Multiple bump electrodes are coupled electrically to each of the electrode layers via third openings formed in the second protective film. In pseudo chips, the second openings are formed in the first protective film and the third openings are formed in the second protective film. The insulating film is exposed at the bottom of the second openings coinciding with the third openings. A protective tape is applied to a principal plane to cover the bump electrodes.
    Type: Application
    Filed: October 24, 2016
    Publication date: June 29, 2017
    Inventors: Yuichi OTA, Kentaro KITA, Takehiro OURA, Kohei YOSHIDA
  • Publication number: 20160190022
    Abstract: Degradation of reliability of a semiconductor device is prevented. An electrode pad included mainly of aluminum is formed over a main surface of a semiconductor wafer. Subsequently, a first insulating member and a second insulating member are formed over the main surface of the semiconductor wafer so as to cover the electrode pad, and thereafter an opening portion that exposes a surface of the electrode pad is formed in the first insulating member and the second insulating member by a dry etching method using an etching gas including a halogen-based gas. Thereafter, an oxide film with a thickness of 2 nm to 6 nm is formed over the exposed surface of the electrode pad by performing a heat treatment at 200° C. to 300° C. in an air atmosphere, and then the semiconductor wafer is stored.
    Type: Application
    Filed: October 21, 2015
    Publication date: June 30, 2016
    Inventor: Takehiro OURA