Abstract: A second output wiring and a third output wiring enter into a chip mounting portion while coming across a second side and a third side of the chip mounting portion. The other end portions of the second output wiring and the third output wiring enter into the chip mounting portion are bent toward a fourth side of the chip mounting portion, and are connected to an output pad and an output pad provided along a fourth side of the semiconductor chip. An input wiring extends along the fourth side of the chip mounting portion, is bent from a midstream to enter into the chip mounting portion while coming across the fourth side of the chip mounting portion, and is connected to an input pad provided along the fourth side of the semiconductor chip.

Abstract: A second output wiring and a third output wiring enter into a chip mounting portion while coming across a second side and a third side of the chip mounting portion. The other end portions of the second output wiring and the third output wiring enter into the chip mounting portion are bent toward a fourth side of the chip mounting portion, and are connected to an output pad and an output pad provided along a fourth side of the semiconductor chip. An input wiring extends along the fourth side of the chip mounting portion, is bent from a midstream to enter into the chip mounting portion while coming across the fourth side of the chip mounting portion, and is connected to an input pad provided along the fourth side of the semiconductor chip.

Abstract: A circuit for driving a liquid crystal display includes decoders for receiving input data to display, and output amplifiers correspondingly connected to the decoders for selectively driving display cells. In each output amplifier, the gate electrodes of a first transistor forming one input of a differential amplifier and a second transistor larger than the first transistor are selectively connected or disconnected when input data changes logical state. The drain electrodes of a third transistor forming the other input of the differential amplifier and a fourth transistor larger than the third transistor are selectively connected or disconnected when the input data changes logical state. The differential amplifier output is selectively fed back to the second transistor to charge or discharge the second transistor. Delay on the output of the decoders is reduced to thereby minimize delay on the output of the output amplifiers.

Abstract: An output circuit of a level shifter or an operational amplifier which converts input signal voltages to different voltage levels. A pMOS transistor PT.sub.2 and nMOS transistor NT.sub.2 connected in series between the power source and ground constitute the output node ND.sub.12. A Wilson mirror is made of pMOS transistors PT.sub.3 -PT.sub.6. An nMOS transistor NT.sub.3 induces a current flow in the current mirror, and an nMOS transistor NT.sub.1 connected between the current output node ND.sub.1 of the current mirror and ground. The gate of pMOS transistor PT.sub.2 is connected to the current output node ND.sub.1, and the gates of nMOS transistor NT.sub.1 and nMOS transistors NT.sub.2 and NT.sub.3 are connected to the input line of signals IN and XIN, which are 180.degree. out of phases.