Abstract: An operating method of a semiconductor device including a NOR type flash memory and a NAND type flash memory is improved. A flash memory includes a NOR type flash memory, a NAND type flash memory, a controller, and an internal bus connecting the NOR type flash memory and the NAND type flash memory to the controller. The controller controls the NOR type flash memory, or the NOR type flash memory and the NAND type flash memory based on a command received from an outside.

Abstract: A flash memory that improves the reliability of data stored in a memory cell array is provided in the disclosure. A wear leveling method of the flash memory of the disclosure includes the following operation. The memory cell array includes multiple sectors, the method includes the following operation. A region is set for storing a first flag and a second flag in each sector of multiple sectors of the memory cell array. The first flag indicates whether bit correction has occurred, and the second flag indicates whether specific data is stored. The second flag of a source sector among the sectors in which the specific data is stored is set. The specific data is written to a new sector among the sectors in which the first flag is in a reset state, and the second flag of the new sector is set.

Abstract: The flame retardant foam is a molded form of a mixture containing at least a cellulose containing powder, a hydrophilic polymer, a foamable thermoplastic resin, a flame retardant, and water. The mixture contains at least one of tricalcium phosphate or silica as a dispersant.

Abstract: A non-transitory, computer-readable recording medium having stored therein a program for causing a computer to execute a process including: parts to be placed on a periphery of a printed-circuit board are placed in a first state, extracting first information for indicating an electrical-connection relationship between the printed-circuit board and the parts based on shape information for indicating shapes of the parts, placement information for indicating placement positions of the parts, and material information for indicating materials of the parts; when the parts are placed in a second state different from the first state, extracting second information for indicating an electrical-connection relationship between the printed-circuit board and the parts based on the shape information, placement information for indicating placement positions of the parts, and material information for indicating materials of the parts; extracting parts of the parts having a different electrical-connection relationship between

Abstract: A flame retardant foam having a high insulation property and excellent flame retardancy and a manufacturing method of the flame retardant foam are provided. The flame retardant foam is a molded form of a mixture containing a cellulose containing powder, a hydrophilic polymer, a foamable thermoplastic resin, a flame retardant, and water. The mixture contains at least one of tricalcium phosphate and silica as a dispersant.

Abstract: A non-transitory, computer-readable recording medium having stored therein a program for causing a computer to execute a process of when parts to be placed on a periphery of a printed-circuit board are placed in a first state, extracting first information for indicating an electrical-connection relationship between the printed-circuit board and the parts based on shape information for indicating shapes of the parts, placement information for indicating placement positions, and material information for indicating materials; when the parts are placed in a second state different from the first state, extracting second information for indicating an electrical-connection relationship between the printed-circuit board and the parts based on the shape information, placement information for indicating placement positions, and material information for indicating materials; extracting parts having a different electrical-connection relationship between the first information and the second information; and outputting a d

Abstract: A stepping motor drive device includes: a first pulse generation circuit that generates pulses at rising or falling edges of a first clock signal; a second pulse generation circuit that generates pulses at rising and falling edges of a second clock signal; a first mask circuit that outputs or masks the output of the first pulse generation circuit depending on whether the second clock signal is normal; a second mask circuit that outputs or masks the output of the second pulse generation circuit depending on whether the first clock signal is normal; a logic circuit that logically combines the outputs of the mask circuits; a step position control circuit that determines the step position of a motor according to the output of the logic circuit; and a motor drive section that supplies a current to the motor according to the output of the step position control circuit.

Abstract: A stepping motor drive device includes: a first pulse generation circuit that generates pulses at rising or falling edges of a first clock signal; a second pulse generation circuit that generates pulses at rising and falling edges of a second clock signal; a first mask circuit that outputs or masks the output of the first pulse generation circuit depending on whether the second clock signal is normal; a second mask circuit that outputs or masks the output of the second pulse generation circuit depending on whether the first clock signal is normal; a logic circuit that logically combines the outputs of the mask circuits; a step position control circuit that determines the step position of a motor according to the output of the logic circuit; and a motor drive section that supplies a current to the motor according to the output of the step position control circuit.

Abstract: A semiconductor device of the present invention includes: a power input terminal; an internal power supply circuit that converts a voltage supplied from the outside to the power input terminal into a predetermined voltage; an analog circuit connected to an output side of the internal power supply circuit; an internal power output terminal connected to the output side of the internal power supply circuit; a logic circuit power input terminal; a logic circuit connected to the logic circuit power input terminal; and interterminal wiring connecting the internal power output terminal to the logic circuit power input terminal. The internal power supply circuit has a configuration of supplying power to the analog circuit and the logic circuit, and in a package assembly (finished product), a resting current in the logic circuit can be inspected without being influence by a consumption current in the analog circuit.

Abstract: An output buffer circuit of the present invention includes: a first output circuit having a first upper switching element and a first lower switching element, the first upper switching element having main terminals, one of the main terminals being maintained at a first voltage, the first lower switching element having main terminals, one of the main terminals being connected to the other main terminal of the upper switching element, the other main terminal of the first lower switching element being maintained at a second voltage, a portion where the other main terminal of the first upper switching element and one of the main terminals of the first lower switching element are connected to each other constituting an output portion for output to outside; a second output circuit having an output terminal connected to the output portion of the first output circuit; and a short-circuit detecting circuit configured to detect a short circuit of the output portion of the first output circuit.

Abstract: There are provided upper and lower switching elements 1U to 1W and 2U to 2W for energizing motor drive windings 4U to 4W, a control circuit 20 that starts outputting a control signal for energization based on an energization instruction, pre-drive circuits 8U to 8W and 9U to 9W for controlling ON/OFF of the upper and lower switching elements based on the control signal, and short circuit detection circuits 10U to 10W for detecting short circuits in a node 14 between the upper and lower switching elements to higher-potential and lower-potential power sources based on the control signal and a voltage of the node.

Abstract: A semiconductor device includes a phase compensation circuit 6 using a MOS capacitor with a structure in which an insulating film is disposed between a gate electrode formed on a semiconductor substrate and a diffusion layer. The phase compensation circuit includes first and second MOS capacitors 14, 15. A gate electrode terminal of the first MOS capacitor is connected equivalently to a diffusion layer terminal of the second MOS capacitor that is a terminal opposite to the gate electrode terminal. A potential difference generating element 16 that generates a potential difference by allowing a current to flow therethrough is connected between a diffusion layer terminal of the first MOS capacitor and a gate electrode terminal of the second MOS capacitor. When the MOS capacitors having the voltage dependence are used, e.g.

Abstract: There are provided upper and lower switching elements 1U to 1W and 2U to 2W for energizing motor drive windings 4U to 4W, a control circuit 20 that starts outputting a control signal for energization based on an energization instruction, pre-drive circuits 8U to 8W and 9U to 9W for controlling ON/OFF of the upper and lower switching elements based on the control signal, and short circuit detection circuits 10U to 10W for detecting short circuits in a node 14 between the upper and lower switching elements to higher-potential and lower-potential power sources based on the control signal and a voltage of the node.

Abstract: A semiconductor device of the present invention includes: a power input terminal; an internal power supply circuit that converts a voltage supplied from the outside to the power input terminal into a predetermined voltage; an analog circuit connected to an output side of the internal power supply circuit; an internal power output terminal connected to the output side of the internal power supply circuit; a logic circuit power input terminal; a logic circuit connected to the logic circuit power input terminal; and interterminal wiring connecting the internal power output terminal to the logic circuit power input terminal. The internal power supply circuit has a configuration of supplying power to the analog circuit and the logic circuit, and in a package assembly (finished product), a resting current in the logic circuit can be inspected without being influence by a consumption current in the analog circuit.

Abstract: A semiconductor device includes a phase compensation circuit 6 using a MOS capacitor with a structure in which an insulating film is disposed between a gate electrode formed on a semiconductor substrate and a diffusion layer. The phase compensation circuit includes first and second MOS capacitors 14, 15. A gate electrode terminal of the first MOS capacitor is connected equivalently to a diffusion layer terminal of the second MOS capacitor that is a terminal opposite to the gate electrode terminal. A potential difference generating element 16 that generates a potential difference by allowing a current to flow therethrough is connected between a diffusion layer terminal of the first MOS capacitor and a gate electrode terminal of the second MOS capacitor. When the MOS capacitors having the voltage dependence are used, e.g.