Abstract: A memory device in which a write error can be prevented is provided. The memory device includes a NAND cell unit including a plurality of memory cells connected in series, a first selection transistor connected to one of terminals of the NAND cell unit, a second selection transistor connected to the other of the terminals of the NAND cell unit, a source line connected to the first selection transistor, and a bit line which intersects with the source line and is connected to the second selection transistor. In the memory device, a channel region of each of the first selection transistor and the second selection transistor is formed in an oxide semiconductor layer.

Abstract: A highly reliable structure for high-speed response and high-speed driving of a semiconductor device, in which on-state characteristics of a transistor are increased is provided. In the coplanar transistor, an oxide semiconductor layer, a source and drain electrode layers including a stack of a first conductive layer and a second conductive layer, a gate insulating layer, and a gate electrode layer are sequentially stacked in this order. The gate electrode layer is overlapped with the first conductive layer with the gate insulating layer provided therebetween, and is not overlapped with the second conductive layer with the gate insulating layer provided therebetween.

Abstract: Provided is a semiconductor device in which an oxide semiconductor layer is provided; a pair of wiring layers which are provided with the gate electrode layer interposed therebetween are electrically connected to the low-resistance regions; and electrode layers are provided to be in contact with the low-resistance regions, below regions where the wiring layers are formed.

Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.

Abstract: In a transistor including a wide band gap semiconductor layer as a semiconductor layer, a wide band gap semiconductor layer is separated into an island shape by an insulating layer with passivation properties for preventing atmospheric components from permeating. The edge portion of the island shape wide band gap semiconductor layer is in contact with the insulating film; thus, moisture or atmospheric components can be prevented from entering from the edge portion of the semiconductor layer to the wide band gap semiconductor layer.

Abstract: To provide a memory element, a memory device, and a semiconductor device, which can be easily manufactured at low cost; are nonvolatile and data-rewritable; and have preferable switching properties and low operating voltage. A memory element of the invention includes a first conductive layer, a second conductive layer facing the first conductive layer, and an organic compound layer provided between the first and the second conductive layers. For the organic compound layer, a high molecular material having an amide group at least at one kind of side chains is used.

Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.

Abstract: A memory device in which a write error can be prevented is provided. The memory device includes a NAND cell unit including a plurality of memory cells connected in series, a first selection transistor connected to one of terminals of the NAND cell unit, a second selection transistor connected to the other of the terminals of the NAND cell unit, a source line connected to the first selection transistor, and a bit line which intersects with the source line and is connected to the second selection transistor. In the memory device, a channel region of each of the first selection transistor and the second selection transistor is formed in an oxide semiconductor layer.

Abstract: The latch circuit includes a transistor whose channel region is formed with an oxide semiconductor (OS). Data is held in a node that is electrically connected to an output terminal and one of a source and a drain of the transistor and brought into a floating state when the transistor is turned off. Note that the oxide semiconductor has a band gap wider than silicon and an intrinsic carrier density lower than silicon. By using such an oxide semiconductor for the channel region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized.

Abstract: To provide a memory element, a memory device, and a semiconductor device, which can be easily manufactured at low cost; are nonvolatile and data-rewritable; and have preferable switching properties and low operating voltage. A memory element of the invention includes a first conductive layer, a second conductive layer facing the first conductive layer, and an organic compound layer provided between the first and the second conductive layers. For the organic compound layer, a high molecular material having an amide group at least at one kind of side chains is used.