Patents by Inventor Takehisa SUGIMOTO

Takehisa SUGIMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240092924
    Abstract: The present invention provides an antibody that binds to an NTCP, capable of inhibiting infection of human hepatocytes with hepatitis B virus (HBV) particles. The present invention also provides an antibody that binds to an NTCP, capable of inhibiting infection of human hepatocytes with hepatitis B virus (HBV) particles, the antibody having a reduced effect on bile acid transport by NTCP.
    Type: Application
    Filed: October 7, 2020
    Publication date: March 21, 2024
    Inventors: Toshitada TAKEMORI, Akiko SUGIMOTO, Michishige HARADA, Mikako SHIROUZU, Takehisa MATSUMOTO, Tomomi SOMEYA, Hiroyuki OSADA, Yushi FUTAMURA, Kunitada SHIMOTOHNO, Hironori NISHITSUJI, Kazuaki CHAYAMA, Daiki MIKI
  • Patent number: 10175518
    Abstract: There are provided a display device including a highly reliable wiring having excellent adhesion to an insulating film, and a method for manufacturing the same. A molybdenum-niobium layer has good adhesion to an insulating film, and thus, a first wiring having the molybdenum-niobium layer as an upper layer wiring is tightly adhered to a gate insulating film which is formed on the surface of the upper layer wiring. When there is a need to exchange a semiconductor chip mounted on a connection terminal that is provided at an end portion of a wiring such as a gate lead line or a source lead line formed of the first wiring, an ACF which was used for pressure-bonding of the semiconductor chip remains on the connection terminal even if the semiconductor chip is peeled off.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: January 8, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hidenobu Kimoto, Tetsuya Tarui, Yoshihiro Seguchi, Takehisa Sugimoto
  • Patent number: 9869917
    Abstract: An active matrix substrate in a liquid crystal panel of an FFS mode has a data line 24 including an amorphous Si film 122, an n+amorphous Si film 123, a main conductor part 133, and an IZO film 141. The main conductor part 133 and the IZO film 141 are etched at a portion close to the end of a covered region of a photoresist 142, to form the n+amorphous Si film 123 larger than the main conductor part 133 and the IZO film 141. A pattern of a photomask for a source layer is made larger than a pattern of a photomask for a pixel electrode layer, to form the amorphous Si film 122 larger than the n+amorphous Si film 123. The main conductor part 133 is formed of a molybdenum-based material, and in a layer over the data line 24, two-layered protective insulating films are formed such that a compressive stress is generated in one film and a tensile stress is generated in the other film. Accordingly, a high-yield active matrix substrate having a common electrode is provided.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 16, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hidenobu Kimoto, Tetsuya Tarui, Yoshihiro Seguchi, Takehisa Sugimoto
  • Publication number: 20170139260
    Abstract: There are provided a display device including a highly reliable wiring having excellent adhesion to an insulating film, and a method for manufacturing the same. A molybdenum-niobium layer has good adhesion to an insulating film, and thus, a first wiring having the molybdenum-niobium layer as an upper layer wiring is tightly adhered to a gate insulating film which is formed on the surface of the upper layer wiring. When there is a need to exchange a semiconductor chip mounted on a connection terminal that is provided at an end portion of a wiring such as a gate lead line or a source lead line formed of the first wiring, an ACF which was used for pressure-bonding of the semiconductor chip remains on the connection terminal even if the semiconductor chip is peeled off.
    Type: Application
    Filed: July 23, 2015
    Publication date: May 18, 2017
    Inventors: Hidenobu KIMOTO, Tetsuya TARUI, Yoshihiro SEGUCHI, Takehisa SUGIMOTO
  • Publication number: 20170139296
    Abstract: A first wiring of the present invention is a wiring having a two-layer structure including a lower layer wiring and an upper layer wiring which is formed to cover an upper surface and both side surfaces of the lower layer wiring, and thus, even if the lower layer wiring includes a part where the line width is reduced and which is nearly disconnected due to a particle or the like attached at the time of formation of the lower layer wiring, the probability is extremely low that a particle is attached again, to the upper layer wiring at the time of formation of the upper layer wiring, at a position corresponding to the nearly disconnected part of the lower layer wiring. Moreover, the lower layer wiring and the upper layer wiring are electrically connected to each other.
    Type: Application
    Filed: July 23, 2015
    Publication date: May 18, 2017
    Inventors: Hidenobu KIMOTO, Tetsuya TARUI, Yoshihiro SEGUCHI, Takehisa SUGIMOTO
  • Publication number: 20170139298
    Abstract: An active matrix substrate in a liquid crystal panel of an FFS mode has a data line 24 including an amorphous Si film 122, an n+amorphous Si film 123, a main conductor part 133, and an IZO film 141. The main conductor part 133 and the IZO film 141 are etched at a portion close to the end of a covered region of a photoresist 142, to form the n+amorphous Si film 123 larger than the main conductor part 133 and the IZO film 141. A pattern of a photomask for a source layer is made larger than a pattern of a photomask for a pixel electrode layer, to form the amorphous Si film 122 larger than the n+amorphous Si film 123. The main conductor part 133 is formed of a molybdenum-based material, and in a layer over the data line 24, two-layered protective insulating films are formed such that a compressive stress is generated in one film and a tensile stress is generated in the other film. Accordingly, a high-yield active matrix substrate having a common electrode is provided.
    Type: Application
    Filed: June 24, 2015
    Publication date: May 18, 2017
    Inventors: Hidenobu KIMOTO, Tetsuya TARUI, Yoshihiro SEGUCHI, Takehisa SUGIMOTO