Abstract: A reactor is provided with a coil including a pair of winding portions arranged in parallel, a magnetic core to be arranged inside and outside the winding portions, a case for accommodating an assembly including the coil and the magnetic core, a leaf spring fitting for pressing the assembly toward an inner bottom surface of the case, and a sealing resin portion to be filled into the case. Each of the winding portions is so arranged that an arrangement direction of the winding portions is along a depth direction of the case. The case includes an opening having a rectangular planar shape. The leaf spring fitting is arranged in a state curved toward the inner bottom surface by having both end parts of the leaf spring fitting directly pressed against parts of inner wall surfaces of the case facing each other in a long side direction.

Abstract: A reactor includes a coil having a winding portion; a magnetic core including an inner core portion and an outer core portion disposed outside the winding portion; a resin cover housing at least a portion of the magnetic core; and an adhesive portion filling a gap between an outer circumferential surface of a housing portion of the magnetic core and an inner circumferential surface of the resin cover bonding the housing portion with the resin cover. The resin cover includes: a flange portion having a surface that comes into contact with an end face of the winding portion and a through hole; an outer cover portion having housing portion housing the outer core portion and an abutting portion that contacts a portion of the flange portion; and a protruding portion that forms the gap between an outer circumferential surface of the outer core portion.

Abstract: A circuit board including a base member, an interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the interconnect layer, and a dielectric layer covering a part of the interconnect layer and an entire surface of the electrically-floating conductive layer and filling a gap between the edge of the interconnect layer and the edge of the electrically-floating conductive layer. In accordance with the present invention, almost all the surface of the base member is covered with the interconnect layer and the floating conductive layer disposed parallel to each other on a substantially single plane. In the circuit board, the moisture does not enter into the rear surface of the dielectric layer through the externally exposed portion to improve the packaging rank.

Abstract: The present invention provides a DNA fragment or promoter for expressing a gene of interest light-repressibly or specifically in the dark. A light-repressible promoter was obtained from the 5? upstream region of a plant gene expressed light-repressibly or specifically in the dark, and the function of said promoter was extensively analyzed to reveal a cis-element sequence and a core sequence involved in light-repressible expression. An expression cassette comprising a DNA fragment carrying each of these sequences upstream of a gene of interest can be constructed and transfected into a plant cell or a plant to provide a plant cell or a plant that expresses the gene of interest light-repressibly or specifically in the dark.

Abstract: A circuit board including a base member, an interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the interconnect layer, and a dielectric layer covering a part of the interconnect layer and an entire surface of the electrically-floating conductive layer and filling a gap between the edge of the interconnect layer and the edge of the electrically-floating conductive layer. In accordance with the present invention, almost all the surface of the base member is covered with the interconnect layer and the floating conductive layer disposed parallel to each other on a substantially single plane. In the circuit board, the moisture does not enter into the rear surface of the dielectric layer through the externally exposed portion to improve the packaging rank.

Abstract: A circuit board including a base member, an interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the interconnect layer, and a dielectric layer covering a part of the interconnect layer and an entire surface of the electrically-floating conductive layer and filling a gap between the edge of the interconnect layer and the edge of the electrically-floating conductive layer. In accordance with the present invention, almost all the surface of the base member is covered with the interconnect layer and the floating conductive layer disposed parallel to each other on a substantially single plane. In the circuit board, the moisture does not enter into the rear surface of the dielectric layer through the externally exposed portion to improve the packaging rank.

Abstract: A circuit board including a base member, an interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the interconnect layer, and a dielectric layer covering a part of the interconnect layer and an entire surface of the electrically-floating conductive layer and filling a gap between the edge of the interconnect layer and the edge of the electrically-floating conductive layer. In accordance with the present invention, almost all the surface of the base member is covered with the interconnect layer and the floating conductive layer disposed parallel to each other on a substantially single plane In the circuit board, the moisture does not enter into the rear surface of the dielectric layer through the externally exposed portion to improve the packaging rank.

Abstract: In a semiconductor device, a bus bar (4a) is provided with a projection (9a). Based on a positional relationship between the projection and a metal wire (13a) subjected to the lateral deflection upon resin filling, the metal wire lateral deflection amount is managed. The projection may be provided on a suspension pin or at another portion of a lead frame. A cutout may be provided instead of the projection.

Abstract: In a semiconductor device, semiconductor chips are mounted on two surfaces of a die pad. A lower one of the semiconductor chips has a portion projecting outward from an upper one of the semiconductor chips. The semiconductor chips are connected to integrally molded external connection leads trough wiring members. The lower semiconductor chipping the outwardly projecting portion has, on its surface on the same side as an upper surface of the upper semiconductor chip, pads to be connected to the external connection leads. A semiconductor device lead frame and a method of manufacturing the same are also disclosed.

Abstract: A hybrid leadframe has first conductive leads extending into space over a semiconductor chip and second conductive leads outside the space, the first conductive leads and the second conductive leads are connected through bonding wires to bonding pads on the semiconductor chip, and the first conductive leads are directly adhered to insulating adhesive compound layers spread on predetermined area of the upper surface of the semiconductor device, wherein the second conductive leads are bifurcated so that one of the bifurcated portions is connected through the bonding wire to the bonding pad and the other bifurcated portion is adhered to the insulating adhesive compound layers so as to enhance the stability of the second conductive lead.

Abstract: The resin-molded portion of a semiconductor package encapsulates a semiconductor element mounting portion, inner leads, and a heat dispersion plate. A semiconductor element is mounted on the surface of the semiconductor element mounting portion. The inner leads are arranged around the perimeter of the semiconductor element and are electrically connected to electrodes on the surface of the semiconductor element. The heat dispersion plate has legs, and the semiconductor element mounting portion is arranged to overlap with the heat dispersion plate. A bonding layer composed of thermoplastic resin, thermosetting resin, or low-melting metal is present at least between the heat dispersion plate and the semiconductor element mounting portion. A portion of the legs of the heat dispersion plate is exposed on the bottom surface of the resin-molded portion. Outer leads that are continuous with the inner leads extend outside the resin-molded portion.

Abstract: Internal electrodes and external lead wiring lines are formed on the front surface of a substrate of a semiconductor device, and solder bumps electrically connected to the external lead wiring lines via through holes are provided on the rear surface of the substrate. A first semiconductor chip is mounted on the surface of the substrate, and a second semiconductor chip is mounted on the rear surface of the substrate. Electrodes of the first semiconductor chip are connected to bonding pads at one side ends of the internal wiring lines, and electrodes of the second semiconductor chip are connected to the bonding pads at the other ends of the internal wiring lines and the external lead wiring lines with bonding wires passing through openings provided in the substrate.

Abstract: In a semiconductor device having a lead-on-chip structure, a thin plate is arranged in an outer peripheral area of a semiconductor element and has a thickness substantially the same as that of the semiconductor element.

Abstract: A plastic-encapsulated semiconductor device is provided, which makes it possible to reinforce the power/ground line by a bus-bar without using the over-lead bonding technique.

Abstract: There is provided a semiconductor device sealed therearound with resin, including (a) a lead frame formed with an island region and a plurality of inner leads, tip ends of the inner leads defining a cavity as viewed perpendicularly to a plane of the chip, the island region being located in the cavity, (b) a chip mounted on the island region of the lead frame and having a plurality of electrodes thereon, and (c) wires for connecting the electrodes of the chip to the inner leads. The cavity is defined so that a wire for connecting inner leads to electrodes located at corners on a diagonal line D1 of the chip is shortest in length and a wire for connecting one of electrodes located at a corner on a diagonal line D2 perpendicular to the diagonal line D1 is longest in length.

Abstract: A molding die for sealing a semiconductor element with a resin includes an upper and a lower mold half. A leadframe having a resin passage aperture is sandwiched between the lower mold half and the upper mold half. The lower mold half has a lower runner space, a lower cavity, and a lower gate provided between the lower runner space and the lower cavity. The upper mold half has an upper resin well, an upper cavity, and an upper gate provided between the resin well and the upper cavity. The length of the upper resin well in the direction of the flow of resin is equal to or greater than the distance from the lower gate to the front edge of a lower runner rising slope, to thereby obtain a final product which is free from resin burrs formed in the upper resin well.