Abstract: Integrated circuit design and operation techniques are disclosed. In some embodiments, a data store stores, for each of a plurality of cores, a core image data comprising metadata about or otherwise associated with the core. A processor receives an indication of an application-related objective and uses core image data stored in the data store to identify programmatically a set of two or more cores from among the plurality of cores to help achieve the objective and to configure the two or more cores to help achieve the objective.

Abstract: Integrated circuit design and operation techniques are disclosed. In some embodiments, a data store stores, for each of a plurality of cores, a core image data comprising metadata about or otherwise associated with the core. A processor receives an indication of an application-related objective and uses core image data stored in the data store to identify programmatically a set of two or more cores from among the plurality of cores to help achieve the objective and to configure the two or more cores to help achieve the objective.

Abstract: Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells operate by inhibiting memory accesses when the voltages are not within an acceptable operating range. One embodiment comprises a pipelined processor having logic components which receive power at a first voltage and a set of SRAM cells which receive power at a second voltage. A critical condition detector is configured to monitor the first and second voltages and to determine whether the ratio of these voltages is within an acceptable range. When the voltages are not within the acceptable range, an exception is generated, and an exception handler stalls the processor pipeline to inhibit accesses to the SRAM cells. When the voltages return to the acceptable range, the exception handler resumes the pipeline and completes handling of the exception.

Abstract: Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells operate by inhibiting memory accesses when the voltages are not within an acceptable operating range. One embodiment comprises a pipelined processor having logic components which receive power at a first voltage and a set of SRAM cells which receive power at a second voltage. A critical condition detector is configured to monitor the first and second voltages and to determine whether the ratio of these voltages is within an acceptable range. When the voltages are not within the acceptable range, an exception is generated, and an exception handler stalls the processor pipeline to inhibit accesses to the SRAM cells. When the voltages return to the acceptable range, the exception handler resumes the pipeline and completes handling of the exception.