Abstract: An input buffer circuit with first and second inverters serially connected between an input terminal and an output terminal of the circuit. The input buffer circuit includes a level detector circuit for detecting that the level of a signal inputted to the input terminal is logically unsteady, and an output level holding circuit for detecting the level of a node where the first and second inverters are connected together and controlling the level of the node to maintain the level, when the level detector circuit detects that the level of the signal is logically unsteady.

Abstract: A semiconductor integrated circuit fabrication method for designing and fabricating semiconductor circuit elements on a semiconductor substrate for an LSI comprises the steps of: replacing standard cells with symbolic cells with an one-to-one correspondence; registering the symbolic cells in a library; drawing a circuit diagram for a semiconductor integrated circuit; describing circuit description net statements for the semiconductor integrated circuit; arranging symbolic cells and wiring among the symbolic cells to obtain a symbolic layout based on the circuit diagram and the circuit description net statements; describing a stick diagram by using the symbolic layout; forming a mask pattern by using the stick diagrams; and forming the semiconductor circuit elements and wiring among the semiconductor circuit elements on the semiconductor substrate by using the mask pattern.

Abstract: A semiconductor integrated circuit fabrication method for designing and fabricating semiconductor circuit elements on a semiconductor substrate for a LSI, which comprises the steps of: drawing a semiconductor circuit diagram by arranging standard cells for the semiconductor circuit elements and wiring among the standard cells by using a standard cell design method; describing circuit description net statements based on the semiconductor circuit diagram; arranging and wiring the standard cells to one another; converting the standard cells into symbolic cells with a one-to-one correspondence to generate a symbolic cell layout; generating a stick diagram in accordance with the symbolic cell layout; changing the dimensions of each transistor in the symbolic cell, overlapping contact areas, vias among them, and wires between adjacent transistors in the symbolic cells as a common area, where possible, shortening the length of wire in the transistor, and changing the sliding of the contact area, the vias, and the wi

Abstract: An integrated circuit with circuit layout enabling higher area utilization efficiency and shorter routing lengths, suitable for large-scale integrated, high-speed processing applications. The integrated circuit includes at least one function block for performing desired functions with respect to input data entered in a first direction to produce output data in the first direction; and at least two control blocks for providing control signals for controlling the operations of the function block, in a second direction perpendicular to the first direction, the control blocks being arranged such that the function block is located between two of the control blocks.

Abstract: A DMA controller for supporting a data transfer operation between a first memory and a second memory includes a selector for selecting data stored in the first memory per data unit, a shifting circuit for shifting the data selected by the selector to one direction of required numbers, a F/F (flip-flop) for storing the data shifted by the shifting circuit for every data unit, a feedback circuit for feedback of the stored data by the F/F to the shifting circuit, and a transfer circuit for transferring the data stored in the F/F to the second memory.

Abstract: A bus driver in which at least two P channel MOS transistors and at least two N channel MOS transistors are employed and these are respectively connected in series. A data signal is inputted into a gate of one of the P channel MOS transistors, an inverted input of an enable signal is inputted into a gate of the other of the P channel MOS transistors, the enable signal is inputted into a gate of one of the N channel MOS transistors and the data signal is also inputted into a gate of the other of the N channel MOS transistors. Further, an output signal is outputted from a connection point of the P channel MOS transistors and the N channel MOS transistors. Also disclosed is another embodiment of a bus driver in which an inverted signal of an enable signal is inputted into the other of the P channel MOS transistors through an inverter.

Abstract: Standard cells in which the accurate estimation of the clock routing length and the minimization of the clock routing are possible so that an optimal protection against the malfunctions due to the racing can be schemed. The standard cells includes flip-flop circuits collectively arranged in a region of the substrate; and clock routing for the flip-flop circuits with connections connecting the clock routing and each of the flip-flop circuits at shortest distance.

Abstract: There is disclosed a barrel shifter for providing efficient wiring therein and a compact composition as compared with conventional ones, in which a low-level-input resistor and a high-level-input resistor are arranged in parallel to each other, and low-level-input-bit lines and high-level-input-bit lines are alternately arranged corresponding to both resistors respectively, the width of both the input and output sides of a barrel-shifter main unit are so arranged as to be substantially the same as the width of the respective resistors substantially defined by wiring width of the respective input-bit lines, and a wiring area from the high-level-input resistor is incorporated in the barrel-shifter main unit as well as a wiring area from the low-level-input resistor.

Abstract: Where an N-bit input data is rotated together with a carry bit by an N-bit or more rotate count, the actual rotate count is obtained as a remainder or modulo of x/N+1 (x: rotate count; N: data bit length). The above remainder will not be obtained by simply masking shift signals. Therefore, the remainder is calculated at high speed through hardware including a subtrahend calculator section for calculating (N+1) (i) (i=0, 1, 2, . . . ) and a subtracter section for calculating {x-(N+1) (i)} to obtain a modulo or a remainder representative of an actual rotate count.

Abstract: In a barrel shifter for shifting an input data by a given shift count in response to shift signals through series-connected NMOS transistors, it is impossible to obtain a sufficiently high ("1") or low ("0") level output signal at high response speed because of the presence of a threshold voltage of the NMOS transistor. To overcome this problem, the drain of the rearmost NMOS transistor (the output terminal of the shifter) is precharged to a supply voltage V.sub.DD in response to a precharge signal before an input data is shifted. Thereafter, if the input data changes to a "1" level, the rearmost NMOS transistor is turned off to output the precharged voltage V.sub.DD as the "1" level shifted output data. On the other hand, if the input data is at a "0" level, the rearmost NMOS transistor is turned on to output a ground voltage GND as the "0" level shifted output data.

Abstract: In a barrel shifter, carry-including rotation operation is implemented only by hardware in such a way that: an N-bit data is shifted by a given shift count through selectors in response to shift signals to obtain a 2N-bit shifted data; a carry is inserted behind a least significant bit of the shifted data through AND gates responsive to a carry signal and a carry rotate signal; and logical sums of each of N lower significant bits of the sN-bit shifted data and each of (shifted by one bit in the higher significant direction) (N-1) higher significant bits thereof are found through selectors and OR gates in response to a carry rotate signal to obtain an N-bit rotated data with carry.

Abstract: In a carry adder of Manchester type, a carry is generated for each full adder and transmitted from a less significant bit to a more significant bit via a series-connected pass transistors. To increase the carry transmission speed, a carry skip circuit is usually connected across pass transistors classified as a block. However, since the skip circuit is still connected to turn-on resistances and stray capacitances of the pass transistors, the carry transmission speed is low and unstable. To overcome this problem, the skip circuit is selectively disconnected from the pass transistors, in response to a NAND signal indicative of the absence of carry signals of the full adder in the same block, by means of two mate clocked inverters alternatively activated by two opposite-level clocks .phi. and .phi..

Abstract: In Booth's method of calculating a product of a multiplicand X and a multiplier Y, Y is divided into plural partial multipliers PP.sub.i (Y.sub.i, Y.sub.i+1, Y.sub.i+2); partial products PD.sub.i are formed separately in sequence by multiplying X by each of decoded partial multiplier values V.sub.pp decoded in accordance with Booth theory; and all the partial products PD.sub.i are accumulatively added to obtain the product. To increase the processing speed twice in spite of a relatively simple circuit configuration, two partial products of X and V.sub.pp are formed simultaneously in sequence and added to obtain a partial product sum PS.sub.i, and all the two partial product sums are accumulatively added to obtain a final result.